GRIP Gigabit Rate IPsec

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GRIP Gigabit Rate IPsec
University of Southern CaliforniaInformation
Sciences Institute East3811 N. Fairfax Dr.,
Ste 200Arlington, VA 22203

• Contact Information

Peter Bellowspbellows_at_east.isi.edu(703) 751-3701
Jarda Flidrjflidr_at_east.isi.edu(703) 751-3710
Tom Lehmantlehman_at_east.isi.edu(703) 751-3736
Brian Schottbschott_at_east.isi.edu(703) 751-3722
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GRIP Accelerator 1st Generation
Gigabit Rate Ipsec - research project enabling
end-to-end secure, authenticated communications
at gigabit data rates

• IPSec compliant
• gigabit rate crypto processing/transforms
• development of innovative parallelized, pipelined
  architecture for IP packets processing
• COTS workstation and a PCI based hardware
  accelerator with a GbE network interface
• highly-adaptive, reconfigurable platform for
  conducting future research of high-speed IPSec or
  general cryptographic accelerators

XMACII (Vitesse)
GRIP mezzanine board
Transceiver
Virtex 300 (Xilinx)
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66/64 PCI Board SLAAC1V
SLAAC1V board
Mezzanine Connector (GRIP plugs in here)
Virtex 1000 FPGA (Xilinx)
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Architecture overview
Linux kernel 2.4.x
Modified FreeS/WAN
IP IPsec stack
Encryptor Cores (Virtex 1000 FPGA)
GRIP driver
Ethernet
66/64 PCI
Slaac1v Board
X1
GRIP mezzanine Board
X0
XMACII GbE controller
X2
PCI/GRIP controller (Virtex 1000 FPGA)