Title: Statistical Analysis of SRAM Cell Stability
1Statistical Analysis of SRAM Cell Stability
- Kanak Agarwal, Sani Nassif
- IBM Corporation, Austin
2The Problem
- Growing importance of systematic and random
variability - Random variation can cause large mismatch in the
neighboring devices - Random device mismatch has most significant
impact on yield of SRAM arrays - Many failure mechanisms such as read stability,
write fail, performance, and data retention
failures
3SRAM A Highly Susceptible Design
- Data stored in cross coupled inverters
- Conflicting read and write requirements in cell
design - Retain cell contents during read access and
change them during write operation - Proper cell functionality relies on relative
strengths of various devices in the cell
4SRAM A Highly Susceptible Design
- SRAM cells use the smallest devices
- Small sized devices are more susceptible to
variation due to random dopant fluctuation - SRAM arrays are ubiquitous and contain large
number of cells - A typical 4 MB cache contains 38 million cells
- One failure in the cache requires correct
operation up to 5.44 sigma
R Heald, P. Wang, ICCAD 2004
5Outline of This Talk
- SRAM cell stability analysis theory, models and
simulation results - DC noise margin
- Read stability failures
- Write failures
- Read access failures
Cell failure mechanisms
6Static Noise Margin (SNM)
- SNM is the most popular metric for characterizing
cell stability - Graphical method
- Assumes equal and opposite DC offsets at storage
nodes - How do we interpret SNM for checking cell
stability under read noise, alpha particle
strikes etc. ?
7The Loop Gain Concept
- Cross-coupled inverters form a positive feedback
loop system - Cell is on the verge of instability if its loop
gain in unity - Cell stability can be verified by computing loop
gain
G2
Cell is unstable if G1G2 gt 1
G1
J Lohstroh et al, JSSC 1983
8DC Noise Margin Analysis
- Lets assume cell stores a zero at node L
- Positive DC offset at node Lcauses VL to rise
above zero - Find minimum DC noise that causes cell to lose
its state - Gains of individual inverter stages depend on
corresponding inputs - Express loop gain as function of VL
- Find VL at which loop gain 1
DC noise(NoiseL)
VLg (VR)
Node R
Node L
(VR 1)
(VL 0)
VRf (VL)
9Loop Gain
Forward and feedback stage gain and loop gain as
function of VL
VL(flip) is the minimum DC potential at node L
that flips the cell
10VL(flip) on Butterfly Curves
DC noise margin at node L
11DC Disturbance at Node R
- Negative DC offset (NoiseR) at node R pulls VR
below one - Find minimum DC offset at nodeR that causes cell
to lose its state - Express loop gain asfunction of VR
- Find minimum DC potential at node R that flips
the cell (VR(flip))
VLg (VR)
DC noise(NoiseR)
Node L
Node R
(VL 0)
(VR 1)
VRf (VL)
12DC Disturbance at Node R
DC noise margin at node R
13DC Disturbance at Both Nodes
- Cell is subjected to positive DC noise (NoiseL)
at node L and negative noise (NoiseR) at node R - Express loop gain as function of VL and VR
- Find unity loop gain contour
14DC Disturbance at Both Nodes
- Loop gain 1 contour intersects butterfly curves
at VL(flip) and VR(flip) - Model unity loop gain criteria
- Coefficients a and b canbe computed from
VL(flip) and VR(flip) values - Cell stability verified by checking above
constraint
15DC Disturbance at Both Nodes
16Read Stability Failure
- Read operation (Node L stores zero)
- Resistive voltage division between access (AL)
and pull down device (NL) - Disturbance at node L
- If read disturbance is large,cell state can be
flipped - Read stability failure
BR
BL
VL
VR1
PL
NL
AR
AL
PR
NR
WL1
17Read Stability Analysis
- Read operation injects a positive noise at node L
- Analyze read stability by the loop gain method
- Compute noise margin during read operation (RNM)
VL at which loop gain 1
Forward stage
Feedback stage
18Read Noise Margin (RNM)
- RNM is a useful metric in analyzing read
stability - Negative RNM represents a cell flip during read
19Read Stability Failure Probability
- Model RNM distribution as Gaussian
- Linear function of random threshold voltage
variation in all six transistors -
- Read stability fail probability
20Write Failures
- Write operation
- Resistive voltage division between access (AR)
and pull up device (PR) pullsnode R low - If write disturbance is small,cell state may not
flip - Write failure
21Write Failure Analysis
- Write fails if the time required to pull node R
low (TW) is more than the word line duration
(TWL) - TW is non-Gaussian
- Transform TW to obtain linearity
- For (a 1), (1/TW) can be modeled as Gaussian
22Write Failure Probability
- Write fail probability
- (1/Tw) can be modeled as linear function of
change in thresholdvoltages
23Read Access Failures
- Contents of the cell cannot be read during word
line duration (TWL) - Not enough bitline differential to trigger sense
amplifier - Different from read stability failures as cell
retains state - Can be modeled like write failures
- Transform access time (TA) to (1/TA)
- Model (1/TA) as linear function of VT variation
in all six transistors
24Read Access Failures
Read access fail probability
25Cell Failure Probability Results
- Find sensitivities of the stability metrics (RNM,
1/TW, 1/TA) to VT variations in all six
transistors - Find individual failure probabilities
- Joint failure probability can also be easily
computed
Sensitivities of Stability Metrics (V-1)
26Summary
- SRAMs are failing...
- Accurate prediction of cell stability and SRAM
array yield is very important - Discussed many cell failure mechanisms
- Hold failures, read stability, writability, and
read access time failures - Proposed new robustness metrics to analyze cell
stability in the presence of random VT variation - Methodology to enable efficient estimation of the
cell failure probability