Paging and Virtual Memory

1
Paging and Virtual Memory
2
Memory management Review

• Fixed partitioning, dynamic partitioning
• Problems
• Internal/external fragmentation
• A process can be loaded only if a contiguous
  memory chunk is available to accommodate the
  process
• Process size is limited by the main memory size
• Advantage simplicity

3
Paging

• Process memory is divided into fixed size chunks
  of the same size, called pages
• Pages are mapped onto frames in the main memory
• Process pages can be scattered all over the main
  memory

4
Paging example
0
0
0
---
1
1
1
---
2
2
2
---
3
3
Process B
Process A
0
7
4
13
1
8
5
14
2
9
6
Free Frame List
3
10
11
12
Process C
Process D
5
Paging support

• Page table maintains mapping of process pages
  onto frames
• Hardware support is needed to support translation
  of relative addresses within a program (logical
  addresses) into the memory addresses

6
Address translation

• Page (frame) size is a power of 2
• with page size 2r, a logical address of lr
  bits is interpreted as a tuple (l,r)
• l page number, r offset within the page
• Page number is used as an index into the page
  table

7
Hardware support
Logical address
Page
Offset
Frame
Offset
Register
Page Table Ptr
Page Table
Offset
Page Frame
P

Frame
Program
Paging
Main Memory
8
Virtual Memory

• Paging makes virtual memory possible
• Logical to physical address mapping is dynamic
• gt It is not necessary that all of the process
  pages be in main memory during execution

9
Benefits

• More processes may be maintained in the main
  memory
• Better system utilization and throughput
• The process size is not restricted by the
  physical memory size the process memory is
  virtual
• But what is the limit anyway?
• Less disk I/O to swap/load programs

10
How does this work?

• CPU can execute a process as long as some portion
  of its address space is mapped onto the physical
  memory
• E.g., next instruction and data addresses are
  mapped
• Once a reference to an unmapped page is generated
  (page fault)
• Page fault interrupt transfers control to the OS
  handler

11
Page Fault Handler

• Put the process into blocking state
• Program disk controller to read the page from
  disk into the memory
• Later on I/O interrupt signals completion
• Resume the process

12
Why is this practical?

• Observation Program branching and data access
  patterns are not random
• Principle of locality program and data
  references tend to cluster
• gt Only a fraction of the process virtual address
  space need to be resident to allow the process to
  execute for sufficiently long

13
Virtual memory implementation

• Efficient run-time address translation
• Hardware support, control data structures
• Fetch policy
• Demand paging page is brought into the memory
  only when page-fault occurs
• Pre-paging pages are brought in advance
• Page replacement policy
• Which page to evict when a page fault occurs?

14
Thrashing

• A condition when the system is engaged in moving
  pages back and forth between memory and disk most
  of the time
• Bad page replacement policy may result in
  thrashing
• Programs with non-local behavior

15
Address translation

• Virtual address is divided into page number and
  offset
• Mapping of virtual pages onto physical frames are
  facilitated by page table(s)
• Forward-mapped page tables (FMPT)
• Inverted page tables (IPT)

Virtual Address
Page Number
Offset
16
Forward-mapped page tables (FMPT)

• Page table entry (PTE) structure
• Page table is an array of the above
• Index is the virtual page number

Frame Number
P
M
Other Control Bits
P present (valid) bit M modified bit
Page Table
Page
Frame
17
Address Translation using FMPT
Virtual address
Page
Offset
Frame
Offset
Register
Page Table Ptr
Page Table
Offset
Page Frame
P

Frame
Program
Paging
Main Memory
18
Handling large address spaces

• One level FMPT is not suitable for large virtual
  address spaces
• 32 bit addresses, 4K (212) page size, 232 / 212
  220 entries 4 bytes each gt
• 4Mbytes resident page table per process!
• What about 64 bit architectures??
• Solutions
• multi-level FMPT
• Inverted page tables (IPT)

19
Multilevel FMPT

• Use bits of the virtual address to index a
  hierarchy of page tables
• The leaf is a regular PTE
• Only the root is required to stay resident in
  main memory
• Other portions of the hierarchy are subject to
  paging as regular process pages

20
Two-level FMPT
page number
page offset
pi
p2
d
10
10
12
21
Two-level FMPT
22
Inverted page table (IPT)

• A single table with one entry per physical page
• Each entry contains the virtual address currently
  mapped to a physical page (plus control bits)
• Different processes may reference the same
  virtual address values
• Address space identifier (ASID) uniquely
  identifies the process address space

23
Address translation with IPT

• Virtual address is first indexed into the hash
  anchor table (HAT)
• The HAT provides a pointer to a linked list of
  potential page table entries
• The list is searched sequentially for the virtual
  address (and ASID) match
• If no match is found -gt page fault

24
Address translation with IPT
Virtual address
page number
offset
frame number
register
ASID
HAT
page number
ASID

hash
Frame

IPT base
HAT base
register
register
IPT
25
Translation Lookaside Buffer (TLB)

• With VM accessing a memory location involves at
  least two intermediate memory accesses
• Page table access memory access
• TLB caches recent virtual to physical address
  mappings
• ASID or TLB flash is used to enforce protection

26
TLB internals

• TLB is associative, high speed memory
• Each entry is a pair (tag,value)
• When presented with an item it is compared to all
  keys simultaneously
• If found, the value is returned otherwise, it is
  a TLB miss
• Expensive number of typical TLB entries 64-1024
• Do not confuse with memory cache!

27
Address translation with TLB
28
Bits in the PTE Present (valid)

• Present (valid) bit
• Indicates whether the page is assigned to frame
  or not
• A reference to an invalid page generates page
  fault which is handled by the operating system

29
Bits in PTE modified, used

• Modified (dirty) bit
• Indicates whether the page has been modified
• Unmodified pages need not be written back to the
  disk when evicted
• Used bit
• Indicates whether the page has been accessed
  recently
• Used by the page replacement algorithm

30
Bits in PTE

• Access permissions bit
• indicates whether the page is read-only or
  read-write
• UNIX copy-on-write bit
• Set whether more than one process shares a page
• If one of the processes writes into the page, a
  separate copy must first be made for all other
  processes sharing the page
• Useful for optimizing fork()

31
Protection with VM

• Preventing processes from accessing other process
  pages
• Simple with FMPT
• Load the process page table base address into a
  register upon context switch
• ASID with IPT

32
Page size considerations

• Small page size
• better approximates locality
• large page tables
• inefficient disk transfer
• Large page size
• internal fragmentation
• Most modern architectures support a number of
  different page sizes
• a configurable system parameter

33
Next Page replacement