Assertion Based Testing

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Assertion Based Testing
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Testing and verification

• Does the design function according to the
  specifications?
• Example

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Traditional approach

• Generate a set of test cases (vectors)
• Apply to the design.. See if the output is
  correct
• I.e. check addition, see if 22 4
• VHDL assert/report statement built to support
  this activity

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Coverage

• How many test cases does it take to check ever
  possible input in a design..
• Percent Coverage of all possible cases
  actually tested
• Number of cases
• Combinational logic 2of inputs
• (combinatorial explosion)
• Sequential logic 2 (of inputs) x (of states)
• (combinatorial nuclear holocaust)
• Input/signal timing verification
• (even harder)
• What coverage is enough?
• Use designers knowledge, generate functional
  test.. etc
• This technique is no longer adequate for complex
  designs

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Assertion based testing

• Verify a design by testing a set of behaviors
  derived from specifications
• Rather that test 224, test ABR.
• Specfic behaviors are called PROPERTIES
• ASSERTIONS are logical statements about properies
  (I.e. always true, never true)

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Examples

• PROPERTIES
• P0 (AB) R when ALUop 0001
• P1 (A-B) R when ALUop 0010
• P2 ALUop ! 1000
• ASSERTIONS
• Assert never Property ALUop 1000
• Assert implication Property (AB) R when ALUop
  0001
• Assert implication Property (A-B) R when ALUop
  0010

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Testing Assertions
clock
DESIGN UNDER TEST
TEST CASE GENERATOR
ASSERTION CHECKER
Design outputs
Design inputs
Generates a new test case on each clock edge
Tests validity of each assertion on each rising
clock edge
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Assertions in HDL designer

• Open Verification library
• Map the library COE1502_OVL into your project. It
  is located at I\1502\COE1502_OVL
• Find the documentation at
• http//www.cs.pitt.edu/don/coe1502/Reference/OVL.
  html
• Each library component implements one type of
  assertion.
• You will need to write VHDL to implement the
  properties to be tested

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Using OVL in your design
Component assert_always instantiated from OVL
library
Property written in embedded block
User defined message string set in generic msg
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Building a Testbench

• A testbench is a structured way of building a
  framework to test your design

HDL designer creates a new block diagram with the
component under test and a new component with the
same inputs and outputs but with the
directionality of each reversed
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Inside the tester component
Test case generator
Outputs to ALU inputs
Inputs from ALU outputs
Assertion checkers Partitioned by functional
block in ALU
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Inside the test case generator
Random Number generators
Fixed 64-bit Component rand64
Set seed value And width
Variable 1-32 bit component randv
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Inside the logic assertion tester
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Testing signed versus unsigned behaviors
--Antecedent Expression    antecedent_expr lt
true when ALUop"1011" else false     
--Consequent Expression    consequent_expr lt
true when ( ( A lt B) AND  (R X"0000_0000_0000_00
01" )) OR ( ( A gt B) AND (R
X"0000_0000_0000_0000" )) else false   
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Testing the Shifters
antecedent_expr1 lt true when ALUop"1110" else
false consequent_expr1 lt true when
(SHR(A,shamt)) R else false   antecedent_expr2
lt true when ALUop"1100" else false consequent_e
xpr2 lt true when (SHL(A,shamt)) R else false  
USE ieee.std_logic_unsigned
USE ieee.std_logic_signed