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Scalable Ion Traps with Monolithically Integrated CMOS Controls

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Dave Ramsey (packaging) Bob Frahm (packaging) Rae McLellan (electronics and system design) ... Dave Leibrandt (design, simulation, testing) Ike Chuang (overall ... – PowerPoint PPT presentation

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Title: Scalable Ion Traps with Monolithically Integrated CMOS Controls


1
Scalable Ion Traps with Monolithically Integrated
CMOS Controls
  • Dick Slusher
  • Rae McLellan
  • CS Pai
  • Bell Laboratories
  • Lucent Technologies

2
Wonderful People
  • Lucent
  • Dick Slusher (ion trap design, testing)
  • CS Pai (fabrication) New Jersey NanoConsortium
    fabrication team
  • John Gates (fabrication)
  • Yee Low (packaging)
  • Dave Ramsey (packaging)
  • Bob Frahm (packaging)
  • Rae McLellan (electronics and system design)
  • MIT
  • Dave Leibrandt (design, simulation, testing)
  • Ike Chuang (overall design, architectures)
  • NIST (now at Ulm)
  • Rainer Reichle
  • Ion groups
  • NIST
  • University of Michigan

3
Alfred Lord Tennyson
  • ---- maybe wildest dreams
  • are but the needful preludes of the truth

4
Any intelligent fool can make things bigger, more
complex, and more violent. It takes a touch of
genius -- and a lot of courage -- to move in the
opposite direction. Albert Einstein
5
Present Ion Traps
6
Non-scaling Ion Trap
7
Scalable Ion Trap Quantum ComputerSystem Design
Measurement
Ion traps
MEMS Optics
Ion/Optics Control Electronics
Classical Computer
System Compatibility of Quantum and
Classical Spatial Pitch Clock Speed Operating
Temperature Power Dissipation
SIMD (Single Instruction on Multiple
Data) Single gate laser - Multiple ion
gates Single cooling laser Multiple ion
traps Single DAC Multiple ion traps
Great for Ions!
8
Linear Trap with Through Wafer Access
RF electrode spacing 150, 125, 100, 75 mm (center
to center)
University of Innsbruck Oxford
9
NIST Quantum CCD Planar Trap Design
Trap axis
Field lines
Cross-section view
Top view
Dave Kielpinski Chris Monroe John Chaiverini Dave
Wineland
rf electrodes
ac electrodes
10
Scalable Ion Trap Quantum Computer Vision
System Compatibility of Quantum Classical
Spatial Pitch, Clock Speed Operating Temperature,
Power Dissipation
Kim, et. al., QIC (2005)
11
Planar Ion TrapScalable Silicon VLSI
RF Electrodes 1mm Thick W/Al 20 mm Wide
p doped Si wafer 0.018 Wcm 6W
CRF/CC 100
12
Electric Fields Above VLSI Planar Ion Trap
Height (mm)
Position (mm)
13
Trap Loading Problems?
VRF 100V Cd Electrode Separation 85 mm RF
frequency W/2p 50MHz Trap frequency wsec /2p
3 MHz Stability parameter q 221/2 wsec/W
0.17
290K
14
Split control electrodes for doppler cooling
V1
V2
-V
V
15
Sources of Johnson noise heating in planar traps
  • Control circuit resistance Rc 20 ?
  • CMOS transmission gates, 10 ?
  • Wiring, 10 ?

?RF
?c
CRF
Rc
Johnson noise in RF drive (heats ions via
parametric process)
Cc
Control electrode sheet resistance ?c/tc 0.03
?/?
RF electrode sheet resistance ?RF/tRF 0.03 ?/?
v
D. Leibrandt, B. Yurke and R. E. Slusher, to be
pub. QIC
16
Ion Heating
Present Trap Data Anomolous heating 1/d4
17
First generation control electrode layout
18
New control electrode layout
  • Eliminating split between RF electrodes reduces z
    Johnson noise heating by a factor of 5
  • Cooling and micro-motion control

19
VLSI Planar Traps
20
(No Transcript)
21
Recess etch of Oxide Below RF Rail
RF rail
Etched oxide
22
RF Drive
Capacitance 4.6 pf Loss tangent 0.0025
  • Limit RF voltage 400 V peak
  • (in air)
  • 300 V (in vacuum)
  • No Outgassing or resnance shift

Al ground plane Q 360 No Al ground plane Q 150
23
First Ion
111Cd 06/23/06 Dan Stick Monroe
Group University of Michigan
24
Linear Trap with Loading Slot
25
Micro-motion
  • Ions not located at the node of the RF electric
    field exhibit driven motion at the RF frequency,
    called micro-motion

Time averaged total pseudo-potential
RF
DC
?x
RF frequency
cooling less efficient quantum logic operations
slower
26
Micro-motion control
y
z

X (mm)
27
Planar Cross Problem
x 0
28
Cross Planar Trap
Rainers Rule d control d ion
29
Present RF Cross
Control electrodes
Ion Height (mm)
Trapping Depth (V)
RF electrode
Transport Dimension (mm)
30
Revised X Trap
100 mm
1 mm
31
Future Designs
R. Reichle
32
Goal 1000 traps/cm2
33
Ion trap layout Bacon/Shor Quantum Error
Correction Turing model
  • Simplest layout ancilla 9 qubits in line

data ion
ancilla ion
Ike Chuang
First operation put in 0011
state same with
34
  • Simplest layout ancilla 9 qubits in line

data ion
ancilla ion
First operation put in 0011
state same with
35
  • Simplest layout ancilla 9 qubits in line

data ion
ancilla ion
First operation put in 0011
state same with
36
  • Simplest layout ancilla 9 qubits in line

data ion
ancilla ion
First operation put in 0011
state same with
37
  • Simplest layout ancilla 9 qubits in line

data ion
ancilla ion
Second operation verify ancilla by comparing
and
38
  • Simplest layout ancilla 9 qubits in line

data ion
ancilla ion
Second operation verify ancilla by comparing
and
39
Evolution Path
Digital Analog Voltage (DAC) source
Dramatic reduction in interconnect density with
vertical Interconnects and CMOS electronics
1000 ion/cm2
Vacuum seal
FSM
CMOS Transmission gate switch
CMOS Logic
Monolithic integration allowed by low T trap
fabrication
40
Initial Estimates
Gate Density Xs, Ts and Loading zones Ion density 1000/cm2
1 CNOT with Steane 7 qubit code Two
Concatenations
150 mm
Chip edge connections 2000 very
difficult Wiring cross talk Wiring
complexity (islands)
50 mm
Control electrodes
41
Transmission Gate
Inverter
Control
n-FET
DAC Voltage In
DAC Voltage Out
p-FET
42
CMOS
  • 0.18 mm rules
  • Electrode voltage limit 1.8 V
  • OK for 50 mm control electrode/ion distances
  • p and n mobilities and FET dimensions limit
    resistance
  • R a L/mW
  • 6 metalization layers
  • 2 for transmission gates
  • 4 for DAC voltage interconnects
  • A bargain _at_ 425k/wafer

43
Waveforms
Control Electrode
Off Chip DACs
Tgates
Vo
High
V1
Low
V2
Sin
V3
Cos
44
Serial In
Serial Out
2b Shift Register
Clock
2
2-4 Decoder
4b latch
Latch
V0
V2
V1
V3
Control Electrode
45
Sequence
1 msec
V2
Serial In
46
4 to 1 Analog Tgate Multiplexor with Serial
Control Logic
Control Electrode Outline 50x50 mm2
Connection to electrode layer
4 p-FETs
4 n-FETs
RC 5W
Inverters
54m x 42m
Shift Register, Decoder and Latch
47
Summary
  • Planar traps work!
  • Monolithic integration of trap and controls
  • SIMD (Single Instruction on Multiple Data)
  • Single gate laser - Multiple ion gates
  • Single cooling laser Multiple ion traps
  • Single DAC Multiple ion traps
  • CMOS Electronics control designs
  • Applications in Reach (100 1000 ions)
  • Quantum repeaters
  • Quantum simulation
  • Worries
  • Immediate concerns
  • High pressure
  • Control electrode lifetimes
  • Charging effects
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