Introduction to CMOS VLSI Design Lecture 1: Introduction, Circuits and layout

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Introduction toCMOS VLSIDesignLecture 1
Introduction, Circuits and layout
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Introduction

• Integrated circuits many transistors on one
  chip.
• Very Large Scale Integration (VLSI) millions of
  logic gates many Mbits of memroy
• Complementary Metal Oxide Semiconductor
• Fast, cheap, low power transistors
• Today How to build your own simple CMOS chip
• CMOS transistors
• Building logic gates from transistors
• Transistor layout and fabrication
• Rest of the course How to build a good CMOS chip

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A Brief History

• 1958 First integrated circuit
• Built by Jack Kilby at Texas Instruments with 2
  transistors
• 2003
• Intel Pentium 4 mprocessor (55 million
  transistors)
• 512 Mbit DRAM (gt 0.5 billion transistors)
• 53 compound annual growth rate over 45 years
• No other technology has grown so fast so long
• Driven by miniaturization of transistors
• Smaller is cheaper, faster, lower in power!
• Revolutionary effects on society

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Annual Sales

• 1018 transistors manufactured in 2003
• 100 million for every human on the planet
• 100B business in 2004

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Invention of the Transistor

• Vacuum tubes ruled in first half of 20th century
  Large, expensive, power-hungry, unreliable
• 1947 first point contact transistor
• John Bardeen and Walter Brattain at Bell Labs

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Transistor Types

• Bipolar transistors
• npn or pnp silicon structure
• Small current into very thin base layer controls
  large currents between emitter and collector
• Base currents limit integration density (power
  dissipation issue)
• Metal Oxide Semiconductor Field Effect
  Transistors
• nMOS and pMOS MOSFETS
• Voltage applied to insulated gate controls
  current between source and drain
• Low power allows very high integration (ideally
  zero static power)

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MOS Integrated Circuits

• 1970s processes usually had only nMOS
  transistors
• Inexpensive, but consume power while idle
• 1980s-present CMOS processes for low idle power

Intel 1101 256-bit SRAM
Intel 4004 4-bit mProc
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Moores Law

• 1965 Gordon Moore plotted transistor on each
  chip
• Fit straight line on semilog scale
• Transistor counts have doubled every 26 months

Integration Levels SSI 10 gates MSI 1000
gates LSI 10,000 gates VLSI gt 10k gates
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Corollaries

• Many other factors grow exponentially
• Ex clock frequency, processor performance

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Silicon Lattice

• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four neighbors

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Dopants

• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts
  poorly
• Adding dopants increases the conductivity
• Group V (Arsenic) extra electron (n-type)
• Group III (Boron) missing electron, called hole
  (p-type)

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p-n Junctions

• A junction between p-type and n-type
  semiconductor forms a diode.
• Current flows only in one direction

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nMOS Transistor

• Four terminals gate, source, drain, body
• Gate oxide body stack looks like a capacitor
• Gate and body are conductors
• SiO2 (oxide) is a very good insulator
• Called metal oxide semiconductor (MOS)
  capacitor

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nMOS Operation

• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF

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nMOS Operation Cont.

• When the gate is at a high voltage
• Positive charge on gate of MOS capacitor
• Negative charge attracted to body
• Inverts a channel under gate to n-type
• Now current can flow through n-type silicon from
  source through channel to drain, transistor is ON

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pMOS Transistor

• Similar, but doping and voltages reversed
• Body tied to high voltage (VDD)
• Gate low transistor ON
• Gate high transistor OFF
• Bubble indicates inverted behavior

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Power Supply Voltage

• GND 0 V
• In 1980s, VDD 5V
• VDD has decreased in modern processes due to
  scaling
• High VDD would damage modern tiny transistors
• Lower VDD saves power (Dynamic power is
  propotional to C.VDD2.f.a)
• VDD 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

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Transistors as Switches

• We can view MOS transistors as electrically
  controlled switches
• Voltage at gate controls path from source to drain

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CMOS Inverter
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CMOS Inverter
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CMOS Inverter
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NOR Gate
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3-input NAND Gate

• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

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3-input NAND Gate

• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

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Complementary CMOS

• Complementary CMOS logic gates
• nMOS pull-down network
• pMOS pull-up network
• a.k.a. static CMOS

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Series and Parallel

• nMOS 1 ON
• pMOS 0 ON
• Series both must be ON
• Parallel either can be ON

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Conduction Complement

• Complementary CMOS gates always produce 0 or 1
• Ex NAND gate
• Series nMOS Y0 when both inputs are 1
• Thus Y1 when either input is 0
• Requires parallel pMOS
• Rule of Conduction Complements
• Pull-up network is complement of pull-down
• Parallel -gt series, series -gt parallel

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Compound Gates

• Compound gates can do any inverting function
• Ex

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Example O3AI

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Example O3AI

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Signal Strength

• Strength of signal
• How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• nMOS pass strong 0
• But degraded or weak 1
• pMOS pass strong 1
• But degraded or weak 0
• Thus nMOS are best for pull-down network

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Pass Transistors

• Transistors can be used as switches

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Pass Transistors

• Transistors can be used as switches

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Transmission Gates

• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well

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Transmission Gates

• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well

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Tristates

• Tristate buffer produces Z when not enabled

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Tristates

• Tristate buffer produces Z when not enabled

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Nonrestoring Tristate

• Transmission gate acts as tristate buffer
• Only two transistors
• But nonrestoring
• Noise on A is passed on to Y

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Tristate Inverter

• Tristate inverter produces restored output
• Violates conduction complement rule
• Because we want a Z output

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Tristate Inverter

• Tristate inverter produces restored output
• Violates conduction complement rule
• Because we want a Z output

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Multiplexers

• 21 multiplexer chooses between two inputs

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Multiplexers

• 21 multiplexer chooses between two inputs

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Gate-Level Mux Design

• How many transistors are needed?

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Gate-Level Mux Design

• How many transistors are needed? 20

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Transmission Gate Mux

• Nonrestoring mux uses two transmission gates

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Transmission Gate Mux

• Nonrestoring mux uses two transmission gates
• Only 4 transistors

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Inverting Mux

• Inverting multiplexer
• Use compound AOI22
• Or pair of tristate inverters
• Essentially the same thing
• Noninverting multiplexer adds an inverter

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41 Multiplexer

• 41 mux chooses one of 4 inputs using two selects

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41 Multiplexer

• 41 mux chooses one of 4 inputs using two selects
• Two levels of 21 muxes
• Or four tristates

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D Latch

• When CLK 1, latch is transparent
• D flows through to Q like a buffer
• When CLK 0, the latch is opaque
• Q holds its old value independent of D
• a.k.a. transparent latch or level-sensitive latch

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D Latch Design

• Multiplexer chooses D or old Q

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D Latch Operation
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D Flip-flop

• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop,
  master-slave flip-flop

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D Flip-flop Design

• Built from master and slave D latches

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D Flip-flop Operation
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Race Condition

• Back-to-back flops can malfunction from clock
  skew
• Second flip-flop fires late
• Sees first flip-flop change and captures its
  result
• Called hold-time failure or race condition

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CMOS Fabrication

• CMOS transistors are fabricated on silicon wafer
  using the lithography process,
• On each step, different materials are deposited
  or etched
• Easiest to understand by viewing both top and
  cross-section of wafer in a simplified
  manufacturing process

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Inverter Cross-section

• Typically use p-type substrate for nMOS
  transistors
• Requires n-well for body of pMOS transistors

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Well and Substrate Taps

• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
  connection
• Use heavily doped well and substrate contacts /
  taps

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Inverter Mask Set

• Transistors and wires are defined by masks
• Cross-section taken along dashed line

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Detailed Mask Views

• Six masks
• n-well
• Polysilicon
• n diffusion
• p diffusion
• Contact
• Metal

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Fabrication Steps

• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

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Oxidation

• Grow SiO2 on top of Si wafer
• 900 1200 C with H2O or O2 in oxidation furnace

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Photoresist

• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

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Lithography

• Expose photoresist through n-well mask
• Strip off exposed photoresist

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Etch

• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone nasty stuff!!!
• Only attacks oxide where resist has been exposed

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Strip Photoresist

• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesnt melt in next step

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n-well

• n-well is formed with diffusion or ion
  implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si

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Strip Oxide

• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

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Polysilicon

• Deposit very thin layer of gate oxide
• lt 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

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Polysilicon Patterning

• Use same lithography process to pattern
  polysilicon

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Self-Aligned Process

• Use oxide and masking to expose where n dopants
  should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well
  contact

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N-diffusion

• Pattern oxide and form n regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned
  gates because it doesnt melt during later
  processing

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N-diffusion cont.

• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

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N-diffusion cont.

• Strip off oxide to complete patterning step

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P-Diffusion

• Similar set of steps form p diffusion regions
  for pMOS source and drain and substrate contact

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Contacts

• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

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Metalization

• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

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Layout

• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor
  size (and hence speed, cost, and power)
• Feature size f distance between source and
  drain
• Set by minimum width of polysilicon
• Feature size improves 30 every 3 years or so
• Normalize for feature size when describing design
  rules
• Express rules in terms of l f/2
• E.g. l 0.3 mm in 0.6 mm process

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Simplified Design Rules

• Conservative rules to get you started

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Inverter Layout

• Transistor dimensions specified as Width / Length
• Minimum size is 4l / 2l, sometimes called 1 unit
• In f 0.6 mm process, this is 1.2 mm wide, 0.6
  mm long

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Example Inverter
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Example NAND3

• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 VDD rail at top
• Metal1 GND rail at bottom
• 32 l by 40 l

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Stick Diagrams

• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers

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Wiring Tracks

• A wiring track is the space required for a wire
• 4 l width, 4 l spacing from neighbor 8 l pitch
• Transistors also consume one wiring track

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Well spacing

• Wells must surround transistors by 6 l
• Implies 12 l between opposite transistor flavors
• Leaves room for one wire track

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Area Estimation

• Estimate area by counting wiring tracks
• Multiply by 8 to express in l