A probabilistic approach to clock cycle prediction

1
A probabilistic approach to clock cycle
prediction

• J. Dambre,
• D. Stroobandt and J. Van Campenhout
• TAU, December 2, 2002

2
Outline

• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions future work

3
System-level interconnect prediction
Predict length distribution of interconnections
in final implementation
Measured or typical values
Real or hypothetical
4
System-level interconnect prediction
Wire length distribution

• Probabilistic
• wire length variability across multiple layout
  runs
• assumed homogeneous all point-to-point wires
  drawn independently from same distribution
• Not accurate lengths of individual wires for
  particular run!

5
System-level interconnect prediction
Wire length distribution

• Interconnect lengths affect
• routing requirements (cost!)
• power dissipation
• yield
• performance (clock cycle)
• etc. ...

6
System-level interconnect prediction
Wire length distribution

• Assess/compare impact of, e.g.
• new/future technological parameters
• physical design options (e.g. layout or cell
  aspect ratio)
• optimization algorithms that change circuit
  topology
• without having to perform physical design!

7
Outline

• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions future work

8
Prediction of minimal clock cycle
Wire length distribution
Distribution of gate and wire delays
Distribution and expected valueof minimal clock
cycle
9
Previous workprediction of critical path delay
in BACPAC (1)
Wire length distribution
Distribution of gate and wire delays
Distribution and expected valueof minimal clock
cycle
(1) Sylvester et al., SLIP 1999
10
Previous workprediction of critical path delay
distribution (2)
Wire length distribution
Distribution of gatewire delays
Distribution and expected valueof minimal clock
cycle
(2) Iqbal et al., SLIP 2002
11
Prediction of minimal clock cycle?

• Problem minimal clock cycle relates to maximal
  combinatorial delay !
• Maximal logic depth does not model
• equal logic depth, but different number of paths
• paths with less than maximal logic depth can also
  become slowest

gt more important as interconnect represents ever
increasing fraction of total delay !
Need model that captures impact of parallellism
on extreme value !!
12
Outline

• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions future work

13
Prediction of minimal clock cycle?
Distribution of gate and wire delays
Distribution and expected valueof minimal clock
cycle ?

• Available
• gatewire ( segment) delay distribution
• topology of circuit graph
• Assumption
• homogeneous all individual segment delays
  drawn independently from same distribution

14
Prediction of minimal clock cycle
probabilistic principles

• Sum of independent variables?

15
Sum of independent variablespath delay
distribution as a function of logic depth
depth 1
depth 2
depth 4
depth 6
depth 8
depth 10
16
Prediction of minimal clock cycle probabilistic
principles
Maximum of independent variables?
17
Maximum of independent variablesmaximum path
delay distribution for independent paths(logic
depth 4)
1 path
2 paths
8 paths
4 paths
10 paths
6 paths
18
Prediction of minimal clock cycle independent
paths?
Segment delays might be approximately
independent, but paths in a circuit are generally
not independent!
Basic concept of new approach uncoupling of
dependencies!

• Find interconnect topology with
• same number of wire segments
• independent paths only
• approx. same clock cycle distribution

19
Prediction of minimal clock cycle independent
paths?
Definition wire criticality maximal depth of
any path through that wire
20
Prediction of minimal clock cycle independent
paths?
Notion Sensitivity of clock cycle to individual
wire delay strongest on paths with depth wire
criticality

• Approximations
• Ignore impact on clock cycle through paths with
  smaller depth
• Assume that wires with equal criticality have
  equal impact on clock cycle

21
Prediction of minimal clock cycle independent
path model

• Equivalent topology
• find wire criticalities (possible without
  enumeration of all paths !)
• for each depth i equivalent paths(i)
  nets(crit i) / i

22
Outline

• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions future work

23
Prediction of minimal clock cycle
Distribution of segment delays
Distribution and expected valueof minimal clock
cycle
24
Experimental validation

• 68 benchmarks from LGSynth series
• sizes of 527 to 24819 blocks
• logic depths of 6 to 284

Benchmarkcircuits

• Technology parameters from ITRS (ed. 2001,
  technology node 2001)
• Delay models from BACPAC (e.g. Sakurai, Chern,
  ...)

Segment delays

• traditional sum of average segment delays
• new

Measured distribution of maximal path delays
Predicted distribution of maximal path delays
25
Experimental validation
Correlation 0.923 (traditional) 0.959 (new)
26
Experimental validation
Average relative error -29.3 (traditional) 6.7
(new)
27
Outline

• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions future work

28
Validity of assumptions?
Both prediction strategies assume that individual
wire lengths are independent and equally
distributed random variables

• They ignore that
• some wires may almost always be long/short
  (locally different distribution)
• there might be local correlations between wire
  lengths (not independent)

29
Validity of assumptions?
Are deviations due to these assumptions or to
equivalent topology?

• Monte Carlo experiment to meet assumptions
• take measured segment delay distribution
• randomly assign delay from distribution to all
  segments and find maximal path delay
• repeat 1000 times for each circuit
• Only cause of remaining errors can be equivalent
  topology!

30
Assumptions or equivalent topology?
Correlation 0.977 (traditional, vs. 0.923) 0.996
(new, vs. 0.959)
31
Assumptions or equivalent topology?
Average relative error -39.1 (vs. 29.3
) -7.1 (vs. 6.7 )
32
Remaining errors?
Rather systematical underestimation of
approximately 7

• Our equivalent path topology fully uncouples all
  paths.

• But there are alternatives
• with same number of segments,
• also using criticalities,
• for which distributions can be calculated !

33
Remaining errors?

• Example
• measured average clock cycle using segment delay
  distr. from one of the benchmark experiments
• result clock cycle (a) 7.1 below clock cycle
  (b)

Total uncoupling of paths seems too strong! Can
model be tuned to include this effect?
34
Outline

• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions future work

35
Conclusions

• New probabilistic model for clock cycle
  prediction
• captures the essence of circuit parallellism
• based on equivalent graph topology with
  independent paths
• Significantly improved accuracy reached within
  same assumptions as existing work
• Experimentally verified that most of the
  remaining errors are due to these assumptions
• They are OK for many circuits, but very bad for
  some!

36
Future work

• More experiments to validate model sensitivity to
  design options its and usefulness for different
  applications
• Combine model with predicted wire length
  distributions
• Try to find mathematical foundations for
  equivalent topology
• Try to incorporate local effects and study some
  alternative topologies

37
Prediction of minimal clock cycle independent
path model
Non-integer number of paths ?
Paths of equal depth have identical delay
distribution
No problem use non-integer values of m !
38
mm30a an example ...

• Clearly shows inhomogeneity, with many of the
  most critical segments systematically having low
  delays