Lecture 14 VHDL Modeling of Sequential Machines

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Lecture 14 VHDL Modeling of Sequential Machines

• Hai Zhou
• ECE 303
• Advanced Digital Design
• Spring 2002

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Outline

• Describing Sequential Behavior in VHDL
• Latches
• Flip-Flops
• Finite State Machines
• Synthesis Using VHDL
• Using Packages in VHDL
• READING Dewey 17.1, 17.3, 17.4, 17.5, 17.6,
  17.7, 17.8, 17.10, 18.1, 18.2

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Latches

• Latches are easily described by using the
  concurrent signal assignment statement
• entity JK_LATCH is
• port ( J, K in BIT
• Q inout BIT 0
• Q_BAR inout BIT 1)
• end JK_LATCH
• architecture TRUTH_TABLE of JK_LATCH is
• begin
• -- Map truth table into conditional concurrent
  statements
• Q lt Q when (J 0 and K 0) else
• 0 when (J 0 and K1) else
• 1 when (J1 and K 0) else
• Q_BAR
• Q_BAR lt not Q
• end TRUTH_TABLE

J K Q 0 0 Q 0 1 0 1 0
1 1 1 Q/
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Level-sensitive Synchronous Behavior

• When a control signal like a clock controls
  whether the gated latch responds to inputs
• entity JK_GATED_LATCH is
• port ( J, K, CLK in BIT
• Q inout BIT 0
• Q_BAR inout BIT 1) end JK_LATCH
• architecture TRUTH_TABLE of JK_GATED_LATCH is
• begin
• CLKED block (CLK 1) -- guard expression
• begin
• Q lt guarded Q when (J 0 and K 0) else
• 0 when (J 0 and K1) else
• 1 when (J1 and K 0) else
• Q_BAR
• Q_BAR lt not Q
• end block CLKED end TRUTH_TABLE

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Block Statements

• A block statement provides a way to combine a
  group of concurrent statements together
• A group of statements can be placed under a guard
• FORMAT
• label block (guard expression)
• -- declarative part
• begin
• -- statement part
• end block label
• A guard is a boolean expression that evaluates to
  true or false.
• Concurrent statements in block execute if guard
  is true

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Guarded Statement

• A guarded assignment statement executes if either
• (1) the guard expression changes from FALSE to
  TRUE
• (2) The guard expression is TRUE and one of the
  signals appearing on the right hand side of the
  signal assignment changes value
• Example
• B1 block (CONTROL_SIGNAL 1)
• begin
• X lt guarded A or B after 5 min
• Y lt A or B after 5 min
• end blcok B1

5 10 15 20 25 30 35
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Flip-flops

• Edge-triggered flip-flops are controlled by
  signal transitions, latches are controlled by
  levels.
• entity JK_FF is
• port ( J, K, CLK in BIT
• Q inout BIT 0
• Q_BAR inout BIT 1) end JK_LATCH
• architecture DATA_FLOW of JK_FF is
• begin
• CLKED block (CLK 1 and not CLKSTABLE) --
  guard expression
• begin
• Q lt guarded Q when (J 0 and K 0) else
• 0 when (J 0 and K1) else
• 1 when (J1 and K 0) else
• Q_BAR
• Q_BAR lt not Q
• end block CLKED end DATA_FLOW

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Predefined Signal Attributes

• VHDL provides several predefined attributes which
  provide information about the signals
• signal_nameACTIVE indicates if a transaction
  has occurred
• signal_nameQUITE indicates that transaction has
  not occurred
• signal_nameEVENT If an event has occurred on
  signal_name
• signal_nameSTABLE If an event has not occurred
• signal_nameLAST_EVENT Time elapsed since last
  event has occurred
• signal_nameDELAYED(T) A signal identical to
  signal_name but delayed by T units of type TIME

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Setup and Hold Times

• Setup and hold times are timing restrictions
  placed on synchronous sequential systems
• Use assertions in VHDL to describe requirements
• architecture DATA_FLOW of D_FF is
• begin
• assert not
• (CLKDELAYED(HOLD) 1 and
• not CLKDELAYED(HOLD)STABLE and
• not DSTABLE(SETUPHOLD)
• report Setup/Hold Timing Violation
• CLKED block (CLK 1 and not CLKSTABLE)
• Q lt guarded D
• Q_BAR lt not Q
• Q_BAR lt not Q
• end DATA_FLOW

CLK
CLKDELAYED(HOLD)
D
Setup
Hold
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Synchronous Finite State Machines

• Consider example of binary counter

Z0
A
Z1
B
Z2
C
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Data flow VHDL Modeling of Counter

• entity BIN_COUNTER is
• port (CLK in BIT Z out BIT_VECTOR(2 downto
  0))
• end BIN_COUNTER
• architecture DATA_FLOW of BIN_COUNTER is
• type FF_INDEX is (A, B, C)
• type FF_TYPE is array (FF_INDEX) of BIT
• signal Q FF_TYPE
• begin
• DFF block (CLK 1 and not CLKSTABLE) --
  rising edge
• begin -- State D flip flops
• Q(A) lt guarded (Q(A) and not Q(B) ) or (Q(A)
  and not Q(C)) or (not Q(A) and Q(B) and Q(C)
• Q(B) lt guarded Q(B) xor Q(C)
• Q(C) lt guarded not Q(C)
• end block DFF
• -- output function
• Z lt Q(A) Q(B) Q(C)
• end DATA_FLOW

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Algorithmic Modeling of State Machines

• Until now, we showed state machines being modeled
  by data flow (using concurrent statements)
• We will describe using algorithmic or procedural
  form using conventional programming language
  semantics
• process statements
• wait statements
• variable and signal assignments
• if and case statements
• loop statements

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Binary Counter State Diagram
S0 000
S1 001
S7 111
S6 110
S2 010
S5 101
S3 011
S4 100
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VHDL Model of Counter

• architecture ALGORITHM of BIN_COUNTER is
• begin
• process
• variable PRESENT_STATE BIT_VECTOR(2 downto 0)
  B111
• begin
• case PRESENT_STATE is
• when B000 gt PRESENT_STATE B001
• when B001 gt PRESENT_STATE B010
• when B010 gt PRESENT_STATE B011
• when B011 gt PRESENT_STATE B100
• when B100 gt PRESENT_STATE B101
• when B101 gt PRESENT_STATE B110
• when B110 gt PRESENT_STATE B111
• when B111 gt PRESENT_STATE B000
• end case
• Z lt PRESENT_STATE after 10 nsec
• wait until (CLK 1
• end process
• end ALGORITHM

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VHDL Model of FSMs for Synthesis

• One can define a VHDL model of a FSM (Mealy
  Machine) using two processes
• One for the combinational logic for the next
  state and output functions
• One for the sequential elements

Output logic function
Primary inputs
Next state Logic function
Presnt state
Memory elements, FFs
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Architecture Body of FSM
architecture rtl of entname is subtype state_type
is std_ulogic_vector(3 downto 0) constant s0
state_type "0001" constant s1 state_type
"0010" constant s2 state_type "0100"
constant s3 state_type "1000" signal
state, next_state state_type signal con1,
con2, con3 std_ulogic signal out1, out2
std_ulogic signal clk, reset std_ulogic --
process comb logic -- process state registers end
architecture rtl
s0
s1
s2
s3
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Process Statements for Comb/State Reg Logic
when s3 gt if con2 '0' then next_state
lt s3 elsif con3 '0' then out1 lt
'0' next_state lt s2 else
next_state lt s1 end if when others gt
null end case end process
state_logic state_register process (clk,
reset) is begin if reset '0' then
state lt s0 elsif rising_edge(clk) then
state lt next_state end if end process
state_register
begin state_logic process (state, con1, con2,
con3) is begin case state is when s0
gt out1 lt '0' out2 lt '0'
next_state lt s1 when s1 gt
out1 lt '1' if con1 '1' then
next_state lt s2 else
next_state lt s1 end if when s2 gt
out2 lt '1' next_state lt s3

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Use of VHDL in Synthesis

• VHDL was initially developed as a language for
  SIMULATION
• Recently being used as a language for hardware
  synthesis from logic synthesis companies
• Synopsys Design Compiler, Ambit BuildGates,
  Mentor Graphics Autologic, ..
• Synthesis tools take a VHDL design at behavioral
  or structural level and generate a logic netlist
• Minimize number of gates, delay, power, etc.

Area
delay
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Synthesizable Subset of VHDL

• There are a number of constructs that cannot be
  synthesized into hardware
• File operations including textio
• Assertion statements
• There are some generally accepted ways of
  entering VHDL descriptions such that it correctly
  synthesizes the logic

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Use of Packages in VHDL

• A VHDL package is simply a way of grouping a
  collection of related declarations that serve a
  common purpose
• Can be reused by other designs
• package identifier is
• package declaration
• end package identifier

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Predefined Packages

• The predefined types in VHDL are stored in a
  library std
• Each design unit is automatically preceded by the
  following context clause
• library std, work use std.standard.all
• package standard is
• type boolean is (false, true) -- defined for
  operators , lt, gt, ..
• type bit is (0, 1) -- defined for logic
  operations and, or, not
• type character is (..)
• type integer is range IMPLEMENTATION_DEFINED
• subtype natural is integer range 0 to
  integerhigh
• type bit_vector is array(natural range ltgt) of
  bit
• end package standard

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Summary

• Describing Sequential Behavior in VHDL
• Latches
• Flip-Flops
• Finite State Machines
• Synthesis Using VHDL
• Using Packages in VHDL
• NEXT LECTURE Course review