HardwareSoftware Cotesting of Embedded Memories in Complex SOCs

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Hardware/Software Co-testing of Embedded Memories
in Complex SOCs
Baihong Fang Qiang Xu Nicola Nicolici CADT
Research Group McMaster University, Canada
ICCAD 2003
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Purpose

• To investigate a scalable memory BIST
  architecture
• To test both bus-connected memories (BCMs) and
  non-bus-connected memories (NBCMs)
• To develop a power-constrained test scheduling
  algorithm

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Overview

• Challenges of memory built-in self-test (BIST)
• Previous work and motivation
• Proposed memory BIST (MBIST) architecture and
  test scheduling algorithm
• Experimental results
• Conclusion

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Memory BIST Challenges

• Example system-on-a-chip (SOC)
• 8M gate design
• 2 ARM processor cores
• Over 400 BISTed memories
• Testability
• Area and routing overhead
• Resource sharing
• Power constrained scheduling

Source A DFT and Test Generation Methodology
for a Large SoC Design, SNUG Europe 2001
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Test Scheduling Support

• Non-partitioned testing
• Partitioned testing with run to completion

Non-partitioned testing
Partitioned testing with run to completion
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MBIST Architectures

• Standalone MBIST architecture
• High area overhead
• Applicable for testing small number of memories
• Distributed MBIST Architectures
• Software-centric
• No area and performance overhead
• Can only test bus-connected memories (BCMs)
• Long testing time
• Hardware-centric
• Hardware/Software (HW/SW) co-testing

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HW-Centric MBIST Architecture

• Parallel command line
• Dedicated test instruction memory
• Can test heterogeneous memories serially
• Supports non-partitioned test scheduling

Source An effective distributed BIST
architecture for RAMs , ETW 2000
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HW/SW Co-testing MBIST

• Lower the processor performance to the BUS
• Can only test bus-connected memories serially

Source Processor-Programmable Memory BIST for
Bus-Connected Embedded Memories, ASP-DAC 2001
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Motivation

• Architecture
• Distributed with serial interconnect
• Test both BCMs and NBCMs
• Supports partitioned testing with run to
  completion
• Programmable with diagnosis support
• Use hardware/software (HW/SW) co-testing
• Test scheduling algorithm
• Supports test scheduling for both BCMs and NBCMs

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HW/SW Co-Testing MBIST Architecture

• One wrapper for all BCMs
• Wrapper for each NBCM
• Supports partitioned testing with run to
  completion for both BCMs and NBCMs
• Embedded software in on-chip processor

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MBIST Controller

• Standard bus interface to processor
• Parallel interface to BCM wrapper
• Serial interface to NBCM wrappers
• Shared test instruction memory

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NBCM Wrapper

• P1500-like serial interface to controller
• Scan in commands
• Scan out test results

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BCM Wrapper

• Standard bus interface to test all BCMs
• Parallel interface to controller

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Test Scheduling Algorithm

• Supports scheduling of both BCMs NBCMs
• NBCMs wrapped, can be tested concurrently
• BCMs unwrapped, can only be tested serially
• Objective minimize testing time and performance
  and area overhead under given power constraints
• Wrap all BCMs which are not pre-unwrapped
• Unwrap wrapped BCMs that do not affect testing
  time under given power constraints

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Test Scheduling (Example)
100
Power Dissipation
Testing Time
Test Sesson 1
Test Sesson 2
Wr. BCM Wrapped BCM Unwr. BCM Unwrapped BCM
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Test Scheduling (Example)
100
Power Dissipation
Testing Time
Test Sesson 1
Test Sesson 2

• Greedy algorithm M3 unwrap, M6 conflict
• Explore different power, pre-unwrapped BCMs
• Results trade-off among power, area, testing
  time

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Experimental Results (1)

• LEON SOC platform
• SPARC V8 CPU AMBA 2.0 BUS
• 4k I-cache and 4k D-cache
• Wrapped NBCMs
• Unwrapped BCMs

Source http//www.gaisler.com
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Experimental Results (2)

• Total BIST area overhead

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Experimental Results (3)

• Comparisons of different approaches for testing
  BCMs

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Experimental Results (Scheduling)

• Testing time (clock cycles) and wrapper number

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Conclusion

• Proposed a novel distributed MBIST architecture
• HW/SW co-testing for BCMs and NBCMs
• Shared test instruction memory
• Scalable for various embedded memory blocks
• Developed a test scheduling algorithm for both
  BCMs and NBCMs under given power constraints
• Trade-offs between testing time area and
  performance