Corporate Overview

1
Corporate Overview

• Silicon Predictability Designer Productivity
  for
• Better Silicon, Faster

2
Silicon Metrics Mission

• To improve chip performance and shorten design
  cycles by providing characterization and modeling
  technology that provides silicon predictability
  while preserving designer productivity.
• Better Silicon, Faster.

3
Models Drive Design, Analysis, and
VerificationAccuracy and Quality Determine
Product Performance

• Implications of Nanometer Process Technologies
• Issues driving the need for retooling

4
Accurate Performance Prediction is Critical

• Collett International on Timing Issues
• Over 50 of new IC designs in North America
  require 2-4 spins to achieve working silicon.
• 50 of those re-spins are due to timing flaws.
• Sun and Intel on Power Issues
• Sun Microsystems, We dont have the resources to
  fix power problems we have to avoid them.
• Intel, Power is now the limiting factor in
  microprocessor design.
• TSMC on Signal Integrity Issues
• One of the biggest challenges is to ensure
  timing and signal integrity closure.
• Considering these effects during design
  implementation reduces the risk of design failure
  in silicon or unmet performance specifications.

5
Silicon MetricsThe Characterization and Modeling
Company

• Product Breath -- Specified Chip Performance
• Standard Cells, Memories, I/Os and Paths
• Timing, Power and Signal Integrity
• Model Quality -- Fewer Silicon Spins
• Silicon predictability
• SPICE accurate
• EDA Vendor Certified Models
• Characterization Throughput -- Cost Effective
  Model Delivery
• Turn libraries in a day
• Scaleable system to meet characterization needs
• Manage characterization investment vs. model
  requirements

6
SiliconSmart ProductsConsistent Characterization
and Modeling Methodology
Models
Timing Power SI/Noise
7
SiliconSmart CRSophisticated Standard Cell
Characterization and Modeling

• Throughput Low Cost of Ownership
• High-performance platforms (Linux, Sun and HP)
• Scalable distribution architecture
• Optimized simulation-deck generation
• Accuracy Silicon Predictability
• SPICE accurate timing
• State- and path-dependent power
• EDA vendor certified models
• Ease of Use Rapid Implementation
• Automatic functional recognition
• Supports combinatorial, sequential and complex
  cells
• Process-driven user interface
• Built-in model verification

Extracted Cell Netlists
ProcessModels
MeasurementData
ModelVerification
Product Option
Model Formats
8
SiliconSmart SIAdvanced Characterization and
Modeling for Nanometer Design

• Ready Satisfy Designer Needs Now
• First complete SI modeling product
• Supports Synopsys, Cadence and Magma
• Proven Deploy with Confidence
• Chosen by leading library providers
• Jointly developed and certified with Synopsys,
  Cadence and Magma
• Founded on characterization leading SiliconSmart
  technology
• Practical Minimize Total Rollout Cost
• High-throughput incremental solution
• Flexible modeling support levels
• Consistency across multi-platforms

Extracted Cell Netlists
ProcessModels
SiliconSmart CRTiming Power DB
AutomaticConfiguration
Intelligent MeasurementPlanning
Noise Sensitivity
Noise Propagation
Improved Drivers
MeasurementData
Simulation Manager
Level 1
Star-HSpice
Level 2
SmartSpice
Level 3
Spectre
Level 4
Proprietary
Model Formats
Synopsys Liberty
Magma Blast Noise
Cadence ECSM
Cadence CDB
9
SiliconSmart SI The SI Library SolutionWhat
Library Providers Need to Roll Out Support for SI
Tools

• Meets Real SI Needs for Todays Design Teams
• Provides SI models to support latest SI tools
• Enables use of new algorithms to reduce
  noise-related false positives
• Seamlessly Supports Popular Tools and Model
  Formats
• Integrates fully with SiliconSmart CR timing and
  power
• Provides consistent models across design
  platforms
• Helps Library Developers Get to Market Quickly
• Proven solutions available now
• Leverages timing characterization data for fast
  SI setup and turnaround
• Packages our expertise in defining these new
  modeling standards
• Provides Grow Path as SI Needs Evolve
• Full-featured advanced modeling ready when needed
• Benefit from our working relationships with the
  major tool providers
• Cost Effective
• Flexibility to manage characterization investment
  vs. model requirements
• Ability to scale system to meet SI
  characterization needs

10
SiliconSmart IO Comprehensive I/O Model
Development and Analysis

• Throughput Low Cost of Ownership
• Industry standard simulators
• Arc-based distributed processing
• Parallel measurement acquisition
• Accuracy Silicon Predictability
• I/O specific measurements
• Arbitrary I/O topologies
• Mode dependency
• Specification Compliance
• Comprehensive validation of electrical
  specification
• Complete HTML compliance report
• Easy to Use Rapid Implementation
• Automated configuration
• Industry standard model generation

Extracted I/O Netlists
ProcessModels
I/O FunctionDescription
Specification Compiler
AutomaticConfiguration
Interface Specs.
USB 1.0
USB 1.1
USB 2.0
LVDS
SSTL
HSTL
MeasurementData
I2C
PCI
PCI X
Custom
Etc...
11
SiliconSmart MRHigh-Quality Production Ready
Embedded Memory Models

• Throughput Low Cost of Ownership
• High-performance simulators
• Optimized measurement acquisition
• Arc-based distributed processing
• Links to selective extraction
• Accuracy Silicon Predictability
• Consumes entire memory array
• Internal-node constraint measurement
• Dependent constraint acquisition
• Automated slew shifting
• Easy to Use Rapid Implementation
• Process-driven user interface
• Automatic setup for RAMs, ROMs and register files
  
• Eliminates critical path determination
• Automated generation and verification

Extracted Cell Netlists
ProcessModels
Liberty or Tcl Config.
Automatic Configuration
MeasurementData
12
SiliconSmart PATHAutomated SPICE-Accurate
Critical Path Analysis

• Transistor-Level Accuracy
• Full-chip or block analysis
• Leverages cell based methodology
• Comprehensive timing analysis
• High Throughput
• Automatic SPICE deck creation
• Efficient distributed processing
• Automatic STA timing annotation
• Easy to Use
• Integrated with existing STA tools for critical
  path selection
• Automatic path isolation with secondary pin
  conditioning
• Detailed timing path GUI

Extracted Cell Netlists
ProcessModels
AutomaticConfiguration
MeasurementData
Verilog
PrimeTime STA
SPEF
13
SiliconSmart PartnersEDA Tool vendors, Foundries
and IP/Library Vendors
14
The SiliconSmart AdvantageSilicon Predictability
with Designer Productivity

• Specified Chip Performance
• You get better quality timing, power and SI
  analysis results -- minimize guardbanding, get
  higher performance, lower power
• You get lower-cost, higher-margin products --
  better power models for accurate power prediction
• Fewer Silicon Spins
• You get accurate models -- reflecting the true
  silicon behavior
• You minimize the number of place and route
  iterations -- characterization, model publishing
  and exhaustive QA technologies eliminate library
  quality issues
• On-Time, On-Budget Project Delivery
• You start your design sooner, get to place and
  route faster -- early availability of
  high-quality models
• You eliminate the design iteration and silicon
  re-spin costs -- better timing, power and signal
  integrity models

You get Better Silicon, Faster
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www.siliconmetrics.com