Microprocessor system architectures IA32 interrupt handling

1
Microprocessor system architectures IA32
interrupt handling

• Jakub Yaghob

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Overview

• Sources of interrupts and exceptions
• External HW interrupt, asynchronous, maskable
• SW interrupt caused explicitly and synchronous
  using the instructions INTn, INT3 and INTO
• Exception generated by CPU, when it detects
  some error
• Vector system
• IDT (Interrupt Descriptor Table)
• Address and size provided in IDTR
• Each handled event has assigned its vector number
  8-bit number (0-255)
• Exceptions have fixed vector numbers in IA-32
• Assignment of vector numbers for HW interrupts
  leaved on external circuits
• PIC, APIC

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IDT Interrupt Descriptor Table

• IDT
• As a matter of form similar to GDT
• Descriptor table
• Only task-gate, interrupt-gate, trap-gate
• Loading IDTR similar to GDTR
• The size of IDT is max. 2568
• Can be smaller
• In contrast to GDT, the IDT has valid vector
  number 0

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Interrupt handling

• Identify the vector number
• External supplied by interrupt controller using
  a bus protocol
• NMI taken as an exception
• Exception fixed vector number by architecture
• SW interrupt vector number encoded explicitly
  or implicitly in the instructions INTn, INT3 and
  INTO
• Indexing IDT using vector number
• Using a gate in the IDT
• The test EPL DPL for a gate computed only for
  instructions INTn, INT3 and INTO

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Disabling and enabling interrupts

• Only for external maskable HW interrupts
• Changing IF
• Instructions CLI, STI for CPL IOPL
• POPF, silently ignored for CPL gt IOPL
• Task switch, return from interrupt IRET
• Interrupt handling using interrupt-gate
• Masking interrupts and exceptions when switching
  stack
• Atomic change of SSESP
• MOV/POP SS disable external interrupts and debug
  exception until the end of the next instruction
• All other exceptions use the old SSESP

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Priority
7
Gates I
8
Gates II

• Gates behavior
• Nearly the same like the call-gate
• No parameter copying
• EFLAGS automatically stored on the stack
• Changing EFLAGS content
• Clearing flags TF, VM, RF, NT
• Interrupt-gate clears IF
• Some exceptions store error code on the top of
  the stack
• It is the property of an exception, not a gate

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Stack
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Exceptions

• Reserved range of vector numbers 0-31
• Classification
• TRAP
• State report
• Reported immediately after the execution of the
  instruction
• FAULT correctable errors
• Reported before the instruction
• Instruction restart
• ABORT unrecoverable errors
• It is not usually possible to discover the exact
  instruction location
• HW errors
• Inconsistent system tables

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Error code

• EXT external event
• IDT selector from IDT
• TI LDT/GDT (IDT0)

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Exceptions I
13
Exceptions II
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Double fault DF

• The second exception calling an exception handler
  for a prior exception
• Interrupts divided into 3 classes
• Benign 1-7, 9, 16-19, INTn, INTR
• Contributory 0, 10-13
• Page fault 14

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Invalid TSS TS I
16
Invalid TSS TS II
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Page fault PF

• CR2 contains linear address which generated the
  exception
• Conditions
• The P flag in any page table level is cleared
• Insufficient access rights
• Access a page with CPL3 and U/S0
• Write to page with CPL3 and R/W0
• Write to page with CPL0-2 and R/W0 and CR0WP
  0 (from Pentium above)
• Execution from page with NX1
• Any reserved bit set to 1

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Page fault error code
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Exceptions and interrupt handling in the long mode

• Like in 32-bit mode with following exceptions
• All interrupt handlers in IDT are in 64-bit code
• Stack is 64-bit wide
• SSRSP always pushed
• New SS is NULL when CPL changes
• IRET behaves differently (always pops SSRSP)
• New interrupt stack mechanism
• The alignment of stack is different (16-bytes-XMM
  registers)

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Interrupt/trap gate 64b
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Interrupt stack table

• Individually enabled in descriptors
• Part of the 64-bit TSS
• 7 new stacks
• IST0 means old stack mechanism
• Calling interrupt handler
• RSP loaded from TSSIST
• SS forced to NULL with RPL set to the new CPL
• Old SS, RSP, RFLAGS, CS, RIP pushed on the new
  stack