A Novel Via Blockage Model and Its Implications

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A Novel Via Blockage Model and Its Implications
Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha,
and James D. Meindl Monday, June 5th 2000
The 2000 IEEE International Interconnect
Technology Conference
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Outline

• Motivation
• Via Classifications Via Blockage Concept
• Main Assumptions Results
• Case Study
• Via-Limited Chip Size
• Conclusions

The IEEE International Interconnect Technology
Conference, June 5-7 2000
3
Outline

• Motivation
• Via Classifications Via Blockage Concept
• Main Assumptions Results
• Case Study
• Via-Limited Chip Size
• Conclusions

The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Interconnect Needs Design

• Interconnect delay device delay
• Multi-level wiring network design
• Interconnect length distribution - Required area
• Wiring efficiency - Available area

The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Vias Role in Design

• Wiring efficiency components
• Power/Ground, Clock lines
• Non-utilized area
• Reasons for non-utilized area
• Routing tool efficiency
• Via blockage

The IEEE International Interconnect Technology
Conference, June 5-7 2000
6
Why Study Via Blockage ?

• Accuracy of multi-level wiring network design
• Prediction on limits of multi-level metalization
  chip miniaturization
• Quantitative means for routing tools evaluation

The IEEE International Interconnect Technology
Conference, June 5-7 2000
7
Outline

• Motivation
• Via Classifications Via Blockage Concept
• Main Assumptions Results
• Case Study
• Via-Limited Chip Size
• Conclusions

The IEEE International Interconnect Technology
Conference, June 5-7 2000
8
Terminal versus Turn Vias
Terminal vias
Turn vias
TOP VIEW
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Conference, June 5-7 2000
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Terminal Vias

• Connect silicon and metal
• Number fixed
• Responsible for via blockage

Interrupted interconnect
SIDE VIEW
Terminal via
The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Turn Vias

• Internal part of an interconnect
• Number varies subject to minimization
• No extra penalty other than doglegs

Turn vias
TOP VIEW
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Conference, June 5-7 2000
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Sparse versus Dense Vias

• Linterc., avg. vs Inter-via distance

• Dense vias -
• ripple effect
• more impact

• Sparse vias -
• footprint area

TOP VIEW
The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Track Availability Approximation

• Channel routing tracks
• Track approximation of via blockage
• Congested track - wasted area

TOP VIEW
The IEEE International Interconnect Technology
Conference, June 5-7 2000
13
Outline

• Motivation
• Via Classifications Via Blockage Concept
• Main Assumptions Results
• Case Study
• Via-Limited Chip Size
• Conclusions

The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Main Assumptions

• Uniform distribution of terminal vias
• Pair-wise use of X-Y orthogonal metal levels
• Length-based interconnect placement
• Equal probability of terminal locations
• Uniform power lines Clock uses small area

The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Via Distribution

• On upper level of n-th pair
• NV 2 I(LMAX) - I(Ln)
• On lower level of n-th pair
• NV 2 I(LMAX) - I(Ln) - I(Ln-1)

I(l) - cumulative interconnect density function
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2 J.A.Davis et al., TED Vol.45, No.3, p.590,
1998.
The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Via Blockage Factors

• Via blockage factor BV
• BV AV / AC
• Auxiliary factor BV
• BV AV / Aeff
• Aeff AC - APS - ACLK
• Relationship BV BV ( Aeff / AC )

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Conference, June 5-7 2000
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Derivation
Aeff
AV Aeff
2W s ?
NV ( 2XW s ? )

BV
2XW s ?
AC
s - Via covering factor ? - Layout rule unit W -
Metal width X - Inter-via distance
The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Via Blockage Factor Expression
NV ( 2W s ? ) 2
BV
AC
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Conference, June 5-7 2000
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Outline

• Motivation
• Via Classifications Via Blockage Concept
• Main Assumptions Results
• Case Study
• Via-Limited Chip Size
• Conclusions

The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Multi-level Interconnect Designs 10
10 R.Venkatesan et al., ASIC/SOC Con., 1999.
The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Via Numbers on Each Level
Dense Via Confirmation
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Conference, June 5-7 2000
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Via Blockage Factor
Metal Level Number
3 G.A.Sai-Halasz, Proceedings of The IEEE,
Vol.83, No.1, p.18, 1995.
The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Outline

• Motivation
• Via Classifications Via Blockage Concept
• Main Assumptions Results
• Case Study
• Via-Limited Chip Size
• Conclusions

The IEEE International Interconnect Technology
Conference, June 5-7 2000
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How Big Is It?

• Estimate of via number on metal One
• NV ? I ( LMAX )
• Ultimate routable pattern

X 2
AV Aeff
2W s ?
BV,MAX

4W s ?
The IEEE International Interconnect Technology
Conference, June 5-7 2000
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The IEEE International Interconnect Technology
Conference, June 5-7 2000
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Outline

• Motivation
• Via Classifications Via Blockage Concept
• Main Assumptions Results
• Case Study
• Via-Limited Chip Size
• Conclusions

The IEEE International Interconnect Technology
Conference, June 5-7 2000
27
Conclusions

• A physical via blockage model is proposed.
• 1st level has the most severe via blockage, from
  more than 10 up to about 50.
• Via-limited and gate-limited chip sizes are of
  the same order of magnitude.

The IEEE International Interconnect Technology
Conference, June 5-7 2000