Asynchronous Machines

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Asynchronous Machines

• Used slides from Mitch Thornton and Prof. Hintz

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Reduce States
State Assignment
Flip-Flop or Latch Selection
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Asynchronous FSM

• Fundamental Mode Assumption
• Only one input can change at a time
• Analysis too complicated if multiple inputs are
  allowed to change simultaneously
• Circuit must be allowed to settle to its final
  value before an input is allowed to change
• Behavior is unpredictable (nondeterministic) if
  circuit not allowed to settle

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Asynch. Design Difficulties

• Delay in Feedback Path
• Not reproducible from implementation to
  implementation
• Variable
• may be temperature or electrical parameter
  dependent within the same device
• Analog
• not known exactly

Tell my stories how I worked with asynchronous
machines in 1968
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Stable State

• PS present state
• NS next state
• PS NS Stability
• Machine may pass through none or more
  intermediate states on the way to a stable state
• Desired behavior since only time delay separates
  PS from NS
• Oscillation
• Machine never stabilizes in a single state

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Races

• A Race Occurs in a Transition From One State to
  the Next When More Than One Next State Variables
  Changes in Response to a Change in an Input
• Slight Environment Differences Can Cause
  Different State Transitions to Occur
• Supply voltage
• Temperature, etc.

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Races
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Types of Races

• Non-Critical
• Machine stabilizes in desired state, but may
  transition through other states on the way
• Critical
• Machine does not stabilize in the desired state

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Races
PS
if Y2 changes first
if Y1 changes first
desired NS non- critical race
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Asynchronous FSM Benefits

• Fastest FSM
• Economical
• No need for clock generator
• Output Changes When Signals Change, Not When
  Clock Occurs
• Data Can Be Passed Between Two Circuits Which Are
  Not Synchronized
• In some technologies, like quantum, clock is just
  not possible to exist, no clocks in live
  organisms.

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Asynchronous FSM Example
input
next state
present state
y1
y2
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Next State Variables
You can analyze this machine at home
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Asynchronous State Tables
States are either Stable or Unstable. Stable
states encircled with symbol.
Present state Next state, output Next state, output
Present state x0 x1
Q0 Q0,0 Q1,0
Q1 Q2,0 Q1,0
Q2 Q2,0 Q3,1
Q3 Q0, 0 Q3,1
Oscillations occur if all states are unstable for
an input value. Total State is a pair (x, Qi)
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Constraints on Asynchronous Networks
If the next input change occurs before the
previous ones effects are fed back to the input,
the machine may not function correctly. Thus,
constraints are needed to insure proper
operation. Fundamental Mode Input changes only
when the machine is in a stable state. Normal
Fundamental Mode A single input change
occurring when the machine is in a stable state
produces a single output change.
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Example 8.4

Find state table for network
Let Q0 be state when y1 0 and Q1 be state when
y1 1.
Present state Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state 00 01 11 10
Q0 Q0,01 Q0,01 Q0,00 Q1,00
Q1 Q1,10 Q0,10 Q0,10 Q1,10
z1z2
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Example 8.5
Analyze circuit with fundamental model
Present state Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state 00 01 11 10
Q0\ 00 Q2 Q3 Q0 Q1
Q1 01 Q1 Q0 Q0 Q1
Q2 11 Q0 Q0 Q0 Q0
Q3 10 Q3 Q3 Q0 Q0
State Code
State y1,y2
Q0 00
Q1 01
Q2 11
Q3 10
Ask student to do this analysis
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Example 8.5
Analyze circuit without fundamental mode
Present state Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state 00 01 11 10
Q0 Q2 Q3 Q0 Q1
Q1 Q1 Q0 Q0 Q1
Q2 Q0 Q0 Q0 Q0
Q3 Q3 Q3 Q0 Q0
State Code
State y1,y2
Q0 00
Q1 01
Q2 11
Q3 10
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Example 8.6
Design the network for the given state table
using SR-latches Use state assignment
Present state Next state, output Next state, output
Present state x0 x1
Q0 Q0,0 Q1,0
Q1 Q2,0 Q1,0
Q2 Q2,0 Q3,1
Q3 Q0, 0 Q3,1
State Code
State y1,y2
Q0 00
Q1 01
Q2 11
Q3 10
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Example 8.6 (Continued)
Use S when state variable must change from 0 to
1 Use R when state variable must change from 1 to
0 Use s when state variable remains 1 Use r when
state variable remains 0
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Example 8.7 D Flip-Flop
Design the circuit from the state table using
SR-latches
Present state Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state 00 01 11 10
Q0 Q0 Q1 Q0 Q0
Q1 Q0 Q1 Q2 Q2
Q2 Q3 Q2 Q2 Q2
Q3 Q3 Q2 Q0 Q0
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Example 8.8
Derive the state table from the circuit
1s where Set and (present state is 1 and not R)
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Example 8.8 (Continued)
y1,y2 Present state Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
y1,y2 Present state 00 01 11 10
00 Q0 Q0 Q1 Q0 Q0
01 Q1 Q0 Q1 Q1 Q2
11 Q2 Q0 Q2 Q3 Q2
10 Q3 Q0 Q0 Q3 Q3
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Race Conditions - Example 8.9
Race Condition when two or more variable change
at a time Critical Race final state dependent
on order in which the state variables change
Present state Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state 00 01 11 10
Q0 Q1 Q0 Q0 Q3
Q1 Q1 Q1 Q1 Q3
Q2 Q2 Q1 Q2 Q3
Q3 Q1 Q1 Q0 Q3
State Code
State y1,y2
Q0 00
Q1 01
Q2 11
Q3 10
Present state y1,y2 Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state y1,y2 00 01 11 10
Q0 00 01 00 00 10
Q1 01 01 01 01 10
Q2 11 11 01 11 10
Q3 10 01 01 00 10
Input x1,x2 10 ?00 10, 00, 01 ok 10, 11, 01 not
ok.
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Avoiding Race
State Adjacency Diagram
State Adjacency Diagram
Present state Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state 00 01 11 10
Q0 Q1 Q0 Q0 Q3
Q1 Q1 Q1 Q1 Q3
Q2 Q2 Q1 Q2 Q3
Q3 Q1 Q1 Q0 Q3
Q1
Q0
Impossible to have hamming distance of 1 between
all adjacent states. Must add states.
Table from previous page
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Asynchronous Machine Hazards
Steady-State Hazards Occurs when a sequential
network goes to an erroneous state due to gate
delay.
Static-1 Hazard
In (01, Q1) consider input change (00) ? (01)
Present state y1,y2 Input x1,x2 Input x1,x2 Input x1,x2 Input x1,x2
Present state y1,y2 00 01 11 10
Q0 00 01 00 00 10
Q1 01 01 01 01 10
Q2 11 11 01 11 10
Q3 10 01 01 00 10
y?1 x1x2 x1 y1y2 x2 y1y2
y?2 x1x2 x2 y2 x1y1
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Steady-State Hazards
Elimination of Static-1 Hazard
y?1 x1x2 x1 y1y2 x2 y1y2
y?2 x1x2 x2 y2 x1y1 x1 y2
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Hazard Example Feedback Sequential Implementation
Maps resulting from State Table 8.5, Example 8.7
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Essential Hazard

• Essential Hazard
• Erroneous sequential operation that cannot be
  eliminated without controlling delays in the
  circuit.
• Not affected by elimination of combinational
  logic hazards.

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Essential Hazard Example
Caused by multiple paths for x
Starting in stable state Q2 with input 0 ? 1
Present state Input x Input x
Present state 0 1
Q0 00 Q0 Q3
Q1 01 Q0 Q1
Q2 11 Q2 Q1
Q3 10 Q2 Q3
Slow
Students should complete this example in class,
on Friday or at home