32bit Pipelined RISC Processor

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32-bit Pipelined RISC Processor
Group 1
aka Go Us
CS m152b Lab section 1
Alice Wang Ann Ho Jason Fong
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General Review of a Pipelined Processor
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Memory Controller Design

• Design challenge 32-bit processor with 16-bit
  memory interface
• On every memory access, need to get two words
  from memory

32-bit
Solution Clock memory controller twice as fast
as rest of processor Results in a memory access
on the rising and falling edge of the processors
clock cycle
32-bit
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Instruction Format
General instruction format
4 bits remaining 28 bits vary
according to instruction type
R-type instruction
unused
unused
I-type instruction
unused
unused
J-type instruction
unused
unused
   
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R-type instructions
I-type instructions
J-type instructions
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ALU with Multiplier
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Multiplier
Uses a series of shifts and additions
0
0 0 0 0
0 0 0 0 0
0
Example 13 x 11 01101 x 01011
HI
LO
01101
01101
x
01101

0 1 1 0

01101

1
1 1 0 1
1
multiplicand
01011
1
1
multiplier
? ? ?
143
0 0 1 0 0
0 1 1 1 1
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multiplier(more efficient, but more hardware)
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Data Forwarding
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Hardware NOP Insertion
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Data Forwarding and Stall InsertionsObserved
Results

• Sample program Bubble-sort 6 numbers

• Assembler insertion of NOPs
• Machine code size 66 words of memory
• Execution time 750 clock cycles

• Hardware data forwarding and NOP insertion
• Machine code size 35 words of memory
• Execution time 400 clock cycles

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Data Forwarding and Stall InsertionsObserved
Results

• Benefits
• Savings in memory and execution time
• Much simpler assembler
• Drawbacks
• Hardware is now more complex
• Tradeoff between hardware complexity and software
  complexity
• Also demonstrates benefits of understanding the
  underlying architecture when designing an
  assembler

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Conclusion

• Some problems we encountered
• Off by one stage in pipeline
• Lack of experience with VHDL
• Order of bits from memory

• In Conclusion...
• Knowledge from previous courses
• Further research
• Simple RISC processor
• Pipelining
• Multiplier
• Data Forwarding and Hardware NOPs

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References

• Hennessey and Patterson, Computer Organization
  and Design (2nd Ed.), 1998, pages 476-495
• Donaldson, John L., Pipeline Hazards,
• http//occs.cs.oberlin.edu/faculty/jdonalds/317/l
  ecture08.html
• Ercegovac, Intro To Digital Systems
• Institute of Electronics, Information and
  Communication Engineers. "High Speed and Very
  Compact Two's Complement Serial/Parallel
  Multipliers Using Xilinx's FPGA"., Abdelkrim
  Kamel Oudjida 19 Nov. 2002, http//search.ieice.or
  g/2001/pdf/e84-a_5_1339.pdf

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Applause Please
Thank You