ECE 353 Introduction to Microprocessor Systems

1
ECE 353Introduction to Microprocessor Systems
Week 2

• Eric Hoffman

2
Tutorial Reminder
Times Thursday, February 5 ? from 600PM to
730PM or Friday, February 6 ? from 400PM to
530PM Location B540EH, Basement lab across
from B555 Topic Keil uVision3 tutorial Sign-up
sheets outside my office
3
Topics

• Microprocessor Organization
• Organization of Microprocessor Systems
• Endian-ness
• ARM History and Characteristics
• ARM7TDMI Implementation
• ADuC7026 Overview

4
Microprocessor Components

• Register file
• Program counter
• General purpose registers
• Hidden registers
• ALU
• Buses
• Memory interface
• Signal conventions
• Control and timing unit

5
A Simple ?P Architecture

• A less simple architecture

6
Instruction Set Architecture (ISA)

• Complex Instruction Set (CISC)
• Single instructions for complex tasks (string
  search, block move, RMW, etc.)
• Usually have variable length instructions
• Registers have specialized functions
• Reduced Instruction Set (RISC) (load/store)
• Instructions for simple operations only
• Usually fixed length instructions
• Large register sets (Register File based)
• Orthogonal operations vs addressing modes

7
Register Architectures

• Accumulator
• One instruction operand comes from a dedicated
  register (the accumulator) closely coupled to the
  ALU.
• Register-Memory
• Instruction operands can be obtained from both
  registers and memory
• Commonly used in CISC machines
• Load-Store
• All operands must be in general-purpose registers
• Only a very limited number of instructions
  (loads/stores) can touch memory
• Commonly used in RISC machines

8
Microprocessor System Organization

• Memory Architectures
• Von Neumann architecture
• Harvard architecture
• Input/Output (I/O)
• Memory-mapped I/O
• Isolated I/O
• Examples
• Programmers Model
• aka Register View
• Memory Maps

9
Endian-ness

• Byte Ordering for Little Endian vs. Big Endian

10
ARM Ltd

• Founded in November 1990
• Spun out of Acorn Computers
• Designs the ARM range of RISC processor cores
• Licenses ARM core designs to semiconductor
  partners who fabricate and sell to their
  customers.
• ARM does not fabricate silicon itself
• Also develop technologies to assist with the
  design-in of the ARM architecture
• Software tools, boards, debug hardware,
  application software, bus architectures,
  peripherals etc

11
ARM Partnership Model
12
ARM Powered Products
13
ARM Characteristics

• Designed to be a simple, efficient RISC core
• Small die area
• Low power
• Low interrupt latency
• These characteristics enabled ARM to become
  dominant in the cell phone market.
• Most cell phones contain a heterogenous
  multiprocessor SoC with an ARM and a DSP.
• Advanced ARM designs (ARM9,10,11) have become
  much more sophisticated (i.e. Intel Xscale in
  PDAs), but have had less success in penetrating
  other markets where power consumption issues are
  not as severe.

14
ARM7TDMI Implementation

• The ARM7TDMI uses the ARM v4T ISA.
• All instructions are conditional
• The ARM7TDMI is a basic load-store RISC
• Sixteen GP registers (R15-R0) with banking
• Three stage pipeline (FDE)
• No caches
• Support for ARM (32-bit) and Thumb (16-bit)
  instruction sets
• Multiply-accumulate (MAC) unit
• On-chip hardware debug support

15
ARM7TDMI Processor Block Diagram
16
ARM7TDMIProcessor Core
17
Analog Devices ADuC7026

• ARM7TDMI core
• 62kB flash, 8kB SRAM
• In-circuit programmable, JTAG debug
• 41.78MHz PLL with programmable divider
• Little-endian
• Numerous digital peripherals
• GPIO
• Timers (GP x4 and watchdog/wake-up)
• UART/I2C/SPI serial interfaces
• 3-phase PWM
• External memory interface (16-bit multiplexed)
• Analog input/output
• 12 in, 4 out
• Voltage reference and temperature sensor

18
ADuC7026 Block Diagram
19
ADuC7026 Memory Map
20
ADuC7026 Pin-Out (LQFP-80)
21
Assessment

• Team ConcepTest
• In-Class Address Decoding Exercise

22
Wrapping Up

• Tutorials on Thursday/Friday next week
• Week 3 reading is chapters 5, 6.1-6.11, 6.14 from
  the textbook, the ARM7TDMI Technical Reference
  Manual chapter 2, and Supplement 1 (on Learn_at_UW)
• Pre-Quiz 2 to be done by Monday 2/2 before class
• Homework 1 due Wednesday 2/4

23
Team ConcepTest

• A 32-bit word with value 0x54AF8 is stored in
  memory at address 0x00008DC44 in a little-endian
  system. Show the address and contents of each
  byte of memory used.
• What type of operation is described by (PC) ?
  (PC) 0Ch?
• A 20-bit address space has a 32KB RAM at base
  address 38000h, and a 128KB ROM at B0000h. Draw
  and label the memory map.

24
In-Class Exercise

• Design decode logic for the following devices
  with the indicated control inputs
• 64Kx8 ROM (/CS, /OE) at 0x040000
• 1Mx8 RAM (/CS, /OE, /WE) at 0xA00000
• Input Port (/OE) at 0xFXXX00
• Output Port (/WR) at 0x1XXXXX
• In all cases, assume a 24-bit address bus (A230)
  and control signals (/RD, /WR)

25
MIPS Pipeline Diagram
26
Register View of a Simple ?P
aka Von Neumann or Princeton architecture
27
Register View of a Simple ?Pwith Isolated I/O
space
Most microprocessors do NOT have isolated I/O.
The Intel x86 microprocessors do.
28
Register View of a Simple ?P with Separate Code
and Data Memories
aka Harvard architecture