Progress 2252005

1
Progress 2/25/2005

• Zheng Guo
• Professor Borivoje Nikolic
• University of California, Berkeley

2
Problem Variations!

• Global
• Material properties of wafer, resists, etc.
• Lens aberration, flow turbulence, oven
  temperature, etc.
• Implant dose, diffusion time, focus, exposure
  energy, etc.
• Bhavnagarwala, 2004.
• Lg, W, oxide thickness, layer thickness, doping,
  etc.
• Local
• Line Edge Roughness (LER).
• Random dopant fluctuations.
• Statistical fluctuations in number and position
  of dopant atoms in the channel spatially
  uncorrelated.
• Discrete oxide thickness.

3
SRAM Yield Limitations

• Read Stability
• Cell can flip due to increase in the 0 storage
  node above the trip voltage of the other inverter
  during a read.
• Hold Stability
• Data retention current not able to compensate the
  leakage currents.
• Access Time
• Time required to produce a pre-specified ?V
  between the bit lines is higher than the maximum
  tolerable limit.
• Only for floating bit-line implementation with
  voltage sensing amplifiers.
• ?V not a problem for current sensing amplifiers.
• Write Stability
• 1 Storage node may not be reduced below the
  trip point of the other inverter before WL is
  discharged.

Mukhopadhyay et al, 2004
4
Read Stability

• AL operates in parallel to PL and keeps VL
  from ever reaching 0V, the gain in the inverter
  transfer characteristic will decrease, causing a
  reduction in the separation between the butterfly
  curves and thus in SNM.

Bhavnagarwala et al, 2001
5
Bulk-Si MOSFET vs. FinFET

• For sub-20nm regime bulk-Si, SCE control requires
  heavy channel doping (gt1018 cm-3) and heavy
  super-halo implants to control sub-surface
  leakage.
• Carrier mobilities are severely degraded due to
  impurity scattering and a high transverse
  electric field in the on state.
• Increased depletion charge density results in a
  larger depletion capacitance hence sub-threshold
  slope.
• For a given off-state leakage current
  specification, on-state drive current is
  degraded.
• Off-state leakage current is enhanced due
  band-to-band tunneling between the body and
  drain.
• Random dopant fluctuations causing Vt variability
  is another concern.
• SCE can be effectively suppressed by using a
  thin-body transistor structure such as the
  FinFET.
• Allows for gate-length scaling down to the 10-nm
  regime without the use of heavy channel/body
  doping.
• Lower transverse electric field in the on state
  and negligible impurity scattering, hence higher
  carrier mobilities.
• Negligible depletion charge and capacitance,
  which yields a steep sub-threshold slope.
• Elimination of heavy doping in the channel
  minimizes Vt variations due to statistical dopant
  fluctuation effects.
• Vertical channel reduces effects of gate
  line-edge roughness.       

6
Double-gate MOSFET

• Back-gate biasing of a thin-body MOSFET remains
  effective for dynamic control of Vt with
  transistor scaling, and can provide improved
  control of SCE as well.

• Back-gated (BG) MOSFET
• Independent front and back gates
• One switching gate and Vth control gate

Double-gated (DG) MOSFET
7
6T Bulk-Si-Based SRAM Cell
8
6T FinFET-Based SRAM Cell
36 increase in SNM w/ 16.6 area penalty.
9
6T SRAM Cell with Rotation

• Double-Gated (DG) FinFET Architecture with
  Rotation.
• Channel surface along (110) plane for NA and PL.
• Channel surface along (100) plane for NMOS NPD to
  increase ß-ratio.
• 14-15 improvement in SNM with 13.3 area
  penalty.

10
6T SRAM Cell with Feed-back
71 improvement in SNM with 2 area reduction.

• Double-Gated (DG) NPD and PL w/ Back-Gated (BG)
  NA to dynamically increase ß-ratio.
• BG access transistor has weaker current driving
  strength compared to the DG access transistor,
  but the 0 storage node in the 6T design with
  feedback stays closer to VSS than the
  conventional DG design.
• BG access transistors in the 6-T design with
  feedback has more gate overdrive.
• Negligible decrease in the cell read current - no
  performance hit.
• Incurs no area penalty over the conventional DG
  6T SRAM cell design.
• Cell area reduced by 2 due to the disappearance
  of the 80nm gate-poly extension over active
  (fin).
• Motivation from Yamaoka, Hitachi, 2004.

11
4T SRAM Cell Design
Yamaoka, Hitachi, 2004

• Data retention leakage current usually need to be
  at least 1000xIleakage to compensate for the
  widely fluctuating leakage current.
• Data retention leakage current flows on both
  sides but only needs to flow in one side for data
  retention.

12
4T SRAM Cell with Feed-back

• Double-Gated (DG) NPD with Back-Gated (BG) PA to
  dynamically increase compensation current and
  ß-ratio.
• FinFET Channel surface along (110) plane.
• NMOS work-function used for PMOS devices high
  threshold.
• NMOS work-function used for NMOS devices
  nominal threshold.
• 63 improvement in SNM on top of a 17.4 area
  savings.

13
4T SRAM Write Issue

• Directions of ICOMPENSATION may reverse while
  writing to a neighboring cell (cell sharing same
  bit-lines).
• PMOS devices can only pull 1 storage node down
  to Vtp.
• Bit is kept if 1 storage node stays above Vtn.
• Problem alleviated by employ high-Vtp PMOS
  devices.
• NMOS work-function used for PMOS devices high
  threshold.
• NMOS work-function used for NMOS devices
  nominal threshold.
• Write margin improved by increasing PMOS drive
  current.
• Word-line swing increased -200mV to 1V.

14
Statistical Variations

• Statistical variations in TSi and LG.
• 3sLG 3sTSi 10 LG.
• Dopant induced fluctuations, which cause large
  SNM spreads are not included in the bulk devices.

15
Leakage Reduction