A Simple, Passive DrivingPoint Model for RLC Interconnect

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A Simple, PassiveDriving-Point Modelfor RLC
Interconnect

• Chandramouli V. Kashyap
• Byron L. Krauter
• IBM Corp.
• Austin, TX

IBM
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Outline

• Motivation
• Overview of the pi-model for RC
• Driving point model for RLC lines
• Results and future work

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Motivation

• RC models insufficient for predicting
  interconnect delay on some long, low-loss nets
• Nets that require RLC modeling include
• Primary clock distribution trees
• Some long buffered lines and busses

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When does inductance matter?
Big driver, long low-loss line, light load, and
short rise times
Gate delay lt RC interconnect delay lt causal
delay
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Overview of the RC pi model
Y(s)
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Overview of the RC pi model
R
Cf
Cn
Uses first 3 non zero moments of Y(s)
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Gate delay computation for RC Lines
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For RLC Lines?
Y(s)
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For RLC lines?
R
Cf
Cn
Pi model with negative values
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For RLC lines?
Moments
Y(s) Y0 y1s ...
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Gate Delay Computation for RLC Lines
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Some Issues

• Moments are abstract mathematical representations
  
• Lack of circuit intuition
• At least one Pade approximation needed
• Since it is not passive, potentially unstable
  response

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Stability Issue
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Possible solutions

• PRIMA Pileggi et al
• Guarantees a passive reduction which in turn
  guarantees stable response
• Matrix based method does not give a simple
  synthesized circuit
• Directly synthesize a passive circuit
• Brune method rational function, transformers
• Bott-Duffin rational function, large number of
  components

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Our Solution
Directly synthesize a simple, passive circuit
using the first four moments
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Derivation of the Model
guarantees pi model
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Derivation of the Model
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Derivation of the Model
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Derivation of the Model
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Results
Experimental setup
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Results
Clock H tree with and without L
ne
fe
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Results
Clock H tree with 5981 elements
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Results
UL with L6.44nH/cm, C3.28pF/cm, R200ohms/cm
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Results
Tree containing 285 elements and 9 sinks
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Results
Daisy chain topology with 4 sinks
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Results
UL with L6.44nH/cm, C3.28pF/cm, R100ohms/cm
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Future Work

• Use the new driving point model for computing
  Ceff in the internal timing analyzer
• Develop a method for reducing two-port RLC
  interconnects