Timing Issues in IC Design

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Timing Issues in IC Design
Ananth Durbha
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State of the art IC specs AMDs AMD k7 500
MHz, 0.25 micron (expected to be available in
first half of 1999) SUNs ultraSPARC-III 600
MHz, 0.18 micron (First systems to emerge around
early 1999) MIPSs MIPS R12000 300 MHz, 0.25
micron (Volume production started early 1998)
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Transistor count of current ICs SUNs
ultraSPARC-III 16,000,000
transistors (volume production Oct
1999) Digitals Alpha 21364(EV7) 100,000,000
transistors (volume production mid-2000) HPs PA
RISC 8500 120,000,000 transistors (volume
production early 1999) SGIs MIPS R12000
6,900,000 transistors (available from 1998)
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Trend projected by National Technology
Roadmap(1992)
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Transistors are getting smaller and density is
getting larger
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Clock signals need to drive bigger chips at
higher frequencies.
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How long does a circuit take to compute its
function ?
One way to answer this question is to model the
circuit as a network of capacitors and variable
resistors and then run a circuit simulator such
as SPICE. Drawbacks How to determine the
sequence of input waveforms that
manifest the longest delay in the circuit ?
SPICE run involves solving system of differential
eqns of size equal to of
capacitive nodes gt not practical
for large circuits.
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Alternative way is to model the circuit as a
graph of logic gates, where each gate has an
associated delay. Under this model the delay
from an input to an output is the
delay of the longest(in the delay sense)
connected sequence of gates, or
directed path, between input and
output Objective Find the longest path through
the weighted, directed acyclic
graph. Drawback Many paths are false paths.
Eliminating them is
not easy.
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Example of a false path
d
Y
X
c
Z
b
For x -gt a y 1 (1) a -gt b z 1
(2) b -gt c y z 0 (3) but (3)
violates (1) hence x cannot propagate to d.
a
The path in yellow is FALSE path
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With chips having more speed and density than
ever, the ability to get quick feedback on signal
delays during design had threatened to hit a
wall - Gil Bassak, ISD, Aug, 1998
Problem Conventional dynamic timing analyzers
grew agonizingly slow and uncertain due to
increasing circuit complexity. Solution Latest
static timing analysis tools are fast and perform
more thorough timing checks across even the
largest chips.
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Problems in dynamic timing analysis 1.
Identifying the set of input vectors for
which the circuit takes the longest time
to compute output 2. Analysis time for large
chips has stretched into weeks where as
the market time (eg. Chips used in mobile
phone) is only about a year. gt Not
sufficient time to recover high design
costs associated with lengthy analysis.
Problems in static timing analysis 1.
Identifying the longest sensitizable path
(rejecting false paths) is tough. 2. Gives
worst case results as far as coupling
capacitance and other physical effects on
signal lines are concerned. 3. Requires
formal definition of circuit.
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Commercial tools available Dynamic timing
analysis MachTA by Mentor Graphics
Corp Waveformer Pro by SynaptiCAD, Inc Static
timing analysis Pearl Timing Ananlyser by
Cadence Design System, Inc SST Velocity by
Mentor Graphics Corp