High Single

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High Single Digit Growth
'81
'90
'95
'00
'85
'06
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Diversification of Semiconductor Applications
Semiconductor Consumption
1995
2000
2005
2010
2020
Source Samsung
UMPC Ultra Mobile PC, MID Mobile Internet
Device
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Increasing Semiconductor Demand
- Expanding functionalities and demand for
higher performance
Semiconductor Demand in 2007
(/Sys)
N/A
N/A
95
N/A
77
1,025
61
98
33
Source Gartner 2007, iSuppli, Strategy
Analytics 2006
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Major Challenges
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Issue 1) Huge CapEx
- Major challenges for financing future profit
Who can afford to construct new Fabs ?
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Capital cost of a Fab (B)
2.5
0.71.0
0.4
20K wpm
20K wpm
0
6 inch
8 inch
12 inch
18 inch
Source Samsung
WPM Wafer per Month
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Only a Few Fab-rich Players
Who is large enough?
40
31.6
19.8
20
Revenue (B)
12.6
10.1
9.9
9.7
10
7.9
7.5
0
TI
AMD
Intel
TSMC
Toshiba
STMicro
Renesas
Samsung
Source Deutsche Securities 2006
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Evolution of Business Model
IP Vendors
Design
Fabless
IDM, going Fab-lite
Product -focused IDM
Process
Foundry
Manufacturing
Assembly Test
Distribution
OEM
Atomized, but expected to change
Integrated
Source McKinsey, Samsung
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Issue 2) Utilization of Legacy Fabs
(Units Million Wafers/Month)
Memory, MPU, Baseband, Graphic Chip, etc
18 inch
12 inch
8 inch
2.7
30?
5.1
06
15 (Est.)
Source Semico Research 2007, Gartner 2007
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Shrink-Adverse Products
Design Rule (um)
More than Moore
Moores Law
Leading-edge Fab
Time
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Combining Leading Legacy Chips

• Product Examples

Leading-edge Legacy
(System in Package)
Analog Part
90nm Process
Source Samsung
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Issue 3) Process ROI Risks
- Process technology development costs are
continuously increasing - Yield ramp-Up require
s significant time and investment
Process Yield Ramp-Up
Process Development Cost
New equipment materials
Capacity Utilization
(B)
90/65
130
45
32
130nm
1.4y
Process Ramp-Up Cost
90nm
2.1y
65nm
1.8y
45nm
2.4y
Process Development Cost
32nm
2.6y
D/R (nm)
130
90
65
45
32
Time
0
2.0
Source IBS, 2006
Source EE Times 2005, IBS 2006, Samsung
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Technology Alliances
Process Collaboration
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The Need for Collaboration Increases
IP Vendors
EDA Vendors
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Issue 3) Product ROI Risks
- Finding the right applications and product
markets is difficult
Gate count for typical IC design
Design Cost Trend
46.2M
30M
Required Revenue 10x of Design Cost
Software
16M
18M
Validation
Physical
9M
9.2M
Verification
Architecture
130nm
90nm
65nm
Source IBS 2006
Source Samsung
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ASSP Growth
ASSP/ASIC Revenue Forecast
ASIC Design Starts Trend
of Design Start
84
(B)
ASSP
65
37
ASIC
31
26
16
Source Gartner 2007
Source Gartner 2006
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Single Design for Multi-fab Source
- Multi Design / Multi-fab source vs. Single
Design / Multi-fab source
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Optimal System Solution
- Overall system cost and design risks can be
reduced
Single-Chip
Modem
POP Solution

• SOC Integration
• Small form factor
• Reasonable performance

• System-Level Solution
• Small form factor
• High performance

• Also,
• LOW SOC design cost/BOM
• SHORT time-to-market

• But
• HIGH SOC design cost
• LONG time-to-market

OneDRAMTM Integrated DRAM solution supporting
the inter processor memory features
OneNANDTM Flash memory solution covering both
NOR and NAND functions
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Major Challenges
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Issue 4) Fabrication for Nano-scale
90
65
45
32
22
90
65
45
22
16
130
32
100nm
75nm
50nm
25nm
0
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Technology Modeling Solutions
- Modeling new materials, 3D devices and
equipment/topography
Continuum ? Particle modeling
Material modeling
S. Thompson, IEDM06
High-k dielectric

• Diffusion/Act. Kinetic MC
• Transport Full-band MC

Mobility study (Strain, high-k, thin body)
Compact model for 3D devices
Equipment/Topography modeling
Early stage feasibility projection
in product design aspects

• Physically-based depo/etch
• Tighter multi-scale formulation

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Advanced Lithography Modeling
Sub-wavelength Lithography Will continue until 22
nm
Source Mark Bohr, Intel
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Issue 5) Design for Nano-scale
Increasing leakage
Yield decomposition at process nodes
800
SiO2 Lkg
10 mm Die
)
SD Lkg
2
Active
8 MB
400
Power Density (W/cm
4 MB
2 MB
1 MB
Parametric
Required level
0
90nm
65nm
45nm
32nm
Increasing leakage power variation
Systematic
Random
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20X
130nm
90nm
65nm
Source PDF Solutions
Source S. Borkar, Intel
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DFM Solutions in Design Stage
Yield
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Low Power Solutions
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Runtime Proactive Design for Yield
Self-Adaptive Design
Task mapping
Latency e.g., Razor
Phase tuning e.g., PST clk
Voltage (Vdd/Vbb)
Vdd
Ioff
SW
Forward Vbb
No Vbb
Reverse Vbb
CPU
CPU
D
Time
Frequency
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Issue 6) Design Complexity
Increase in chip complexity
Design Complexity
95
03
12
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ESL for Design Complexity
Controller
Hybrid HDD
System-level model of Hybrid HDD
including controller, Flash, DDR, disk, and host
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ESL for Many-Core Design
Current multi-core SOC
Mem
IP
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SIP 3D-LSI Solution
Integration CPU Memory Analog Sensor
Analog
Analog
Memory
Analog
CPU
Memory
CPU
CPU
Silicon
Memory
Good
Better
Best
Better
Good
Best
Better
Best
Good
Better
Good
Best
Better
Good
Best
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Chip/Board Co-design
52degC
47degC
46degC
Hot Spot on Chip
Real Set Analysis
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Vision
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Summary
- Fabrication and design for nano-scale
atomistic level TCAD modeling,
advanced lithography and runtime proactive
design for yield - Design complexity many-core
design and chip/package/board co-design
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