SOI Photonic Crystal Fabrication

1
SOI Photonic Crystal Fabrication

• Stephen Farrell
• MicroPhotonic Devices Group
• Professor John OBrien

2
Presentation Outline

• Introduction and motivation
• Fabrication procedure
• Description of process steps
• Improvements and results
• Conclusion

3
Integrated Photonics
"Today, optics is a niche technology. Tomorrow,
it's the mainstream of every chip that we build."
Patrick Gelsinger Sr. Vice President Digital
Enterprise Group Intel Corporation
4
Photonic Crystals

• Completely engineerable
• High Q cavities
• Small footprint
• Tight turn radii

5
Photonic Crystals in SOI

• When the photonic crystal patterning is complete
  the Au is removed with a wet etch.

• The oxide mask and lower cladding are removed
  with diluted HF. A short oxidation and oxide
  removal serve to smooth the sidewalls in the
  final processing step.

• The Si membrane is patterned with BCl3/Ar
  chemistry in ECR-RIE. The PMMA does not survive
  this step.

• Photonic crystal patterns are written into the
  PMMA resist by e-beam lithography

• The pattern is then transferred to the Au layer

• And developed in a mixture of MiBK and IPA.

• and through the thin (20nm) SiO2 adhesion layer
  by ion beam milling.

6
Electron Beam Lithography

• Photonic crystal patterns generated in a 200nm
  layer of 3 PMMA (diluted in dichlorobenzene)
  positive resist
• Performed with Philips converted thermal emission
  SEM with 10nm spot size

7
Ion-Beam Milling Patterning Au

• Electrons collide with inert gas molecules to
  create positively charged ions
• Ions are accelerated to sputter material from
  sample surface a purely physical phenomenon
• Pressure typically 10-4 torr
• Accelerating voltages usually 500-1000V
• Sample chucks can be rotated and cooled
• Our Iontech, Inc. system has a 10cm ion beam

8
Ion-Beam Milling
Accelerator Grid
An inert gas is delivered to the chamber

Anode

-
Sample
A
e-
A
A
A
e-
e-
Argon
e-
A
e-
Electrons collide with gas atoms
e-
e-
A
A
A
A

-
e-
e-
A
e-
A
Ions are collimated and accelerated
e-
e-
A
A
e-
A
A
A
e-
e-
e-
e-

-
A
e-
A
A
e-
And combine with electrons to give a uniform
potential
e-
-
A
Cathode

-
-
Positive Grid
Neutralizer Filament
-

9
After Ion-Beam Milling
PMMA/Au interface
Au/SiO2 interface
SiO2/Si interface
10
Mill Rates for Several Materials
From R. Williams, GaAs Processing Methods
11
Ion-Beam Milling
12
Reactive Ion Etching

• RF power applied to wafer chuck creates
  oscillating e-field that strips electrons from
  gas molecules
• Electrons respond to fast RF oscillation
  (13.56MHz), but heavy ions do not
• A negative DC bias accumulates, attracting
  positively charged ions to sample surface
• Ions react with surface material, evaporate off
  and are pumped out of the system

13
Reactive Ion Etching
Gas Inlet
An RF source is used to dissociate the molecules
Electrons react more readily to RF oscillations
Positive ions are attracted to negatively biased
sample
e-
e-
e-
e-
e-



e-

e-
e-
RF





e-
e-
e-
e-
e-
e-






e-
e-
e-
e-
e-
e-
-VDC
Sample
To Pump
14
Reactive Ion Etching

• Chamber pressures on the order of millitorr
• Can be very directional (anisotropic)
• Mask selectivities an order of magnitude or
  higher
• Generally used to pattern dielectrics and
  semiconductors
• We have used this technique to etch our SiO2 and
  SiNx masks

15
Electron Cyclotron Resonance

• An enhancement for an RIE system increases
  degree of ionization
• Lorentz force from a static, uniform magnetic
  field causes electrons to move in a circle
• Microwaves absorbed by electrons and heats them
• Low-pressure, almost collision-less plasma
• Resonance frequency is 2.45GHz, B 875G

16
After ECR-RIE Etching
In a chemistry of BCl3 and Ar
Gold Mask
Thin SiO2 Layer
Si Membrane
Buried Oxide
17
Top View of PCWG After Dicing
Dicing trenches
Open Boxes
PCWG
18
After Undercut
SiO2 adhesion layer and buried oxide etched away
with HF acid
19
Directional Coupler
20
Characterizing Our Fabrication
We can fabricate devices with a standard
deviation of 1.5 for r/a
And a standard deviation of 1 for hole radii
21
Tuning of PC hole radii
Diameter
280nm
190nm
22
Control of PC Hole Sizes
d 190nm
d 280nm
r/a 0.341
r/a 0.228
23
PCWG Transmission Data
24
Conclusion

• I have detailed our photonic crystal fabrication
  process in SOI
• I have shown evidence of improvements in device
  quality