Status R

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Status RD CBM Trigger/DAQ Hardware

• Joachim Gläß
• Computer Engineering, University of Mannheim
• Contents
• DAQ Architecture
• Requirements for Hardware
• Steps to Trigger/DAQ Hardware Prototypes
• Status

Oct. 11, 2005 3rd FutureDAQ Workshop
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from Walter Müller, CBM Collaboration Meeting,
Sep. 2005
3
from Walter Müller, CBM Collaboration Meeting,
Sep. 2005
4
RD Prototype for DCB, ABB, L1FPGA
Data Combiner Board (DCB)

• bi-directional (optical) link
• data, trigger, RoI, control, clock
• FPGA
• logic for data (/protocol) processing
• processor for control
• external memory (DDR)
• Ethernet as main control interface

OASE or MGT
OASE or MGT
OASE or MGT
OASE or MGT
FPGA
PPC
Oct. 11, 2005 3rd FutureDAQ Workshop
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RD Prototype for DCB, ABB, L1FPGA
Data Combiner Board (DCB)

• bi-directional (optical) link
• data, trigger, RoI, control, clock
• FPGA
• logic for data (/protocol) processing
• processor for control
• external memory (DDR)
• Ethernet as main control interface
• external memory
• for data storage
• PC interface (PCIexpress)
• Interface to Bnet

Active Buffer Board (ABB)
OASE or MGT
OASE or MGT
OASE or MGT
OASE or MGT
memory
FPGA
PPC
memory
PCIe (MGT)
Oct. 11, 2005 3rd FutureDAQ Workshop
6
RD Prototype for DCB, ABB, L1FPGA
Data Combiner Board (DCB)

• bi-directional (optical) link
• data, trigger, RoI, control, clock
• FPGA
• logic for data (/protocol) processing
• processor for control
• external memory (DDR)
• Ethernet as main control interface
• external memory
• for data storage (DDR)
• for LUT (ZBT)
• PC interface (PCIexpress)
• Interface to Bnet
• Interface to Pnet

Active Buffer Board (ABB)
Hardware Processor (L1FPGA)
OASE or MGT
OASE or MGT
OASE or MGT
OASE or MGT
memory
FPGA
PPC
memory
PCIe (MGT)
Oct. 11, 2005 3rd FutureDAQ Workshop
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Plan for RD Prototypes

• ABB, L1FPGA Hardware Prototype (ca. 2007)
• FPGA e.g. Virtex4FX60 (100?)
• Memory DDR for ABB, ZBT for L1FPGA
• MGT 2.5 10 Gbit/s
• Initialisation, control, PC interface

Oct. 11, 2005 3rd FutureDAQ Workshop
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Plan for RD Prototypes

• ABB, L1FPGA RD Prototype (ca. 2006)
• divide into smaller boards (cost, complexity, )
• interconnect by backplane
• used in demonstrator

backplane
Oct. 11, 2005 3rd FutureDAQ Workshop
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Plan for RD Prototypes

• V4FX Testboard (ca. 2005)
• PPC with external DRAM and Ethernet (Linux)
  Software for control
• Test and classification of MGTs
• optical, copper, backplane,
• Test of OASE
• PCIe interface to PC
• Develop and test RAM controllers
• Develop and test algorithms (shrinked down)

DCB prototype for demonstrator

ABB prototype for demonstrator
backplane connector
OASE
4 x OASE on mezzanine 2 x RAM on
mezzanine Probe on mezzanine
FPGA
OASE
Virtex4FX20
PPC
OASE
OASE
PCIe (MGT)
Oct. 11, 2005 3rd FutureDAQ Workshop
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Status RD Prototypes

• V4FX Testboard (ca. 2005)
• Design and PCB ready
• Problem Virtex4 FX not available
• (information from end of September 2005)

Oct. 11, 2005 3rd FutureDAQ Workshop
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Status RD Prototypes

• Proposal use VirtexIIproX
• PPC with external DRAM and Ethernet
• Test and classification of MGTs
• optical, copper, backplane, (X 2.5 10
  Gbit/s)
• Test of OASE
• PCIe interface to PC
• Develop and test RAM controllers
• Develop and test algorithms (shrinked down)

Oct. 11, 2005 3rd FutureDAQ Workshop
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Conclusion

• CBM Trigger/DAQ
• System Layout
• Hardware Architecture
• RD steps
• Testboard
• RD Prototype
• Prototype
• Problem Availability of Chips
• Plan B of Plan B of Plan B necessary
• FPGA, RAM, Voltage Regulators, Optoelectronics,
  Oscilators,
• minimum package size gt 100

Oct. 11, 2005 3rd FutureDAQ Workshop