I2C: InterIntergrated Circuit A Standard for Serial Communications

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I2C Inter-Intergrated Circuit A Standard for
Serial Communications

• TEAM 10
• David Mohabir Anthony Fields Scott Paladino
• Matthew Christy Matthew Palmer
• March 28th, 2007

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What is I2C?

• Stands for Inter-Integrated Circuit
• Method for data transfer between devices
• Serial connection using only 2 wires
• Optimal for low-speed components

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History of I2C

• Invented by Philips in the early 1980s
• Original purpose was to connect a CPU to
  peripherals in televisions
  
• Memory mapped I/O was too expensive
• Saved money by reducing interconnects and ESD
  susceptibility
  
• Technology was licensed to other companies

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Reducing Interconnects
VS
When speed is not a concern, I2C makes sense!
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HOW DOES IT WORK?

• SCL Serial Clock
• The master device is always in control of the
  clock.
  
• SDA Serial Data
• Either the master or a slave device can put data
  on the bus.
  
• Both SCL and SDA are open-drain outputs

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OPEN-DRAIN EXPLAINED

• Open-drain allows multiple devices to communicate
  bi-directionally on a single wire.
  
• Refers to the drain terminal of a MOSFET
  transistor
  
• A Logic 0 is 0V, while a Logic 1 is High
  Impedance (HI-Z)
  
• Allows for multiple outputs to be connected to
  the same node
  
• External pull-up resistors needed

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Open-Drain Outputs

• A pull-up resistor is connected from VDD to both
  SCL and SDA
  
• Pull-up resistor can range from 1K? to 100k?
• Philips recommends the pull-up resistor be 2.2
  K?
  
• Multiple open-drain outputs connected to the same
  wire along with a pull-up resistor form a NOR
  array
  
• 5V if no output is 0 0V if any output is 0

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The clock and valid data

• Valid data should be on SDA before SCL rises and
  the valid data should remain on SDA until after
  SCL falls.
  
• Only during two special events (called START and
  STOP) should the SDA voltage change while SCL is
  high.
  

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I2C Transfers

• 2 modes standard (
• Fast and standard devices can be mixed, but fast
  devices are throttled
  
• 9 bits are sent for each transfer
• First 8 bits are sent by the transmitter from MSB
  ? LSB
  
• 9th bit is an acknowledge bit sent by the receiver

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Example Transfer
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ACKNOWLEDGE

• If NO slave acknowledges a transfer from the
  master, this is interpreted as an error.
  
• If the master acknowledges a transfer from a
  slave, this is interpreted as a request for the
  slave to send more data.
  
• If there is no acknowledge from the master, this
  is interpreted as a request by the master for the
  slave to stop sending data.

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START and STOP conditions

• START condition
• SDA falls while SCL is high used by master to
  signal that the bus is starting a new
  transaction.
  
• STOP condition
• SDA rises while SCL is high used by master to
  signal that the bus is entering an idle state.
  
• Idle state
• Both SDA and SCL idle high
• Bus is allowed to float to pull-up

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I2C TRANSACTION SEQUENCE

• All transactions begin with a START condition
• The first 9-bit transfer contains a 7-bit slave
  address, a read/write bit, and an ACKNOWLEDGE
  bit
  
• The second 9-bit transfer contains an 8-bit
  memory address in the slave and an ACKNOWLEDEGE
  bit
  
• Zero or more 9-bit transfers follow
• If the bus is to return to idle following the
  transaction, a STOP condition is issued

• A transaction from start to stop is called a
  message string
  

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Identifying Devices

• Each I2C peripheral chip should have a unique
  slave address.
  
• Slave addresses are usually 7-bit but can be
  10-bit in some systems.
  
• Valid 7-bit slave addresses are in the range 0x08
  to 0x77.
  

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Example Write to Slave

• First 9-bit transfer is sent by master with 7-bit
  slave address and R/W 0.
  
• Second 9-bit transfer is sent by master with
  8-bit internal peripheral register number (N)
  that the master wants to write to first.
  
• One or more 9-bit transfers are sent by master
  which the slave writes into internal peripheral
  registers number N, N1, N2, etc.
  
• Writing a set of adjacent registers in a single
  slave can be done with a single transaction.
  

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Example continued
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Initializing a PIC for I2C

• I2C SCL rate to 100 KHz
• SSPADD 0x18
• Make SCL and SDA pins outputs
• TRISC XXX1 1XXX
• Use SSP for I2C in master mode
• SSPCON1 0x38

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I2C CONTROL WITH A PIC

• SSPCON2 register contains 7 bits which start all
  actions except sending an address (slave address
  or internal address) or data for a slave.
  
• SSPBUF is where addresses or data are written and
  where data is read.
  
• Writing to this register automatically initiates
  a 9-bit transfer out of the PIC.
  

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I2C CONTROL CONT.

• Five of the bits (SEN, RSEN, PEN, RCEN, and
  ACKEN) of SSPCON2 start an action when the bit is
  set and are automatically cleared when the action
  completes.
• The ACKDT bit specifies if an acknowledge action
  should be ACK or NOACK by the PIC.
  
• The ACKSTAT bit tells the PIC if the slave gave
  an ACK or a NOACK.
  

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I2C CONTROL

• SEN initiates a START condition if the bus is
  idle.
  
• RSEN initiates a START condition in the middle
  of a message (also called RESTART).
  
• PEN initiates a STOP condition.
• RCEN allow a data byte to be received.
• ACKEN Generates an ACK or a NOACK after
  receiving a byte from a slave.
  
• Whether an ACK is generated or a NOACK is
  generated depends on the current value of ACKDT.
  

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Slave Addressing

• Most I2C parts have a fixed upper byte of the
  slave address
  
• The lower byte is determined by connecting pins
  (A0, A1, etc.) to VDD or ground.
  

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Multi-master Capabilities

• Multiple devices have master priority on the data
  bus
  
• Cooperation between devices is critical to avoid
  having multiple logic levels driving the data
  line
  
• Arbitration logic determines which device will be
  allowed to drive the line
  
• Either the device that writes the most zeros or
  the slowest device
  
• Bus busy detection
• Each device must be able to detect communication
  on the bus
  
• Recognize the communication traffic and wait for
  the stop signal before beginning communication
  
• When using multimaster mode, all masters must be
  multi-master devices
  
• Single master devices do not recognize the
  correct communication procedures and results are
  unpredictable

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Clock Stretching

• Needed when slave devices cannot co-operate with
  the clock signal provided by the master
  
• Clock speed needs to be slowed down
• A slave is allowed to hold the bus low to reduce
  the bus speed
  
• The master reads back the clock signal after
  releasing it to high state and waits for the line
  to go high before continuing clock transmission

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Example of an I2C device

• MAX518 has two analog output pins.
• The slave address is 01011XX where A0 and A1
  select the least-significant bits.
  
• There are two internal addresses, one for each
  analog output pin.
  
• The output voltage is VDD(n/256), where n is the
  internal address value for the pin.
  

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ADVANTAGES OF I2C

• One MCU can control many devices with just two
  I/O pins and software
  
• Hot Swapping
• Due to HI-Z, devices can be added to or removed
  from system while power is on
  
• Less pins and lines ? less

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DISADVANTAGES OF I2C

• Low speed
• In simple configuration, complexity of I2C
  software components can be significantly higher
  than other methods (SPI, CAN, etc)

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Questions?