Game Console Architecture

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Game Console Architecture

• Jeongwon Seo Yongchul Kim

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What is Game Console?

• A video game console is an interactive
  entertainment computer or electronic device that
  manipulates the video display signal of a display
  device (a television, monitor, etc.) to display a
  game.

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PlayStation 2
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CPU for Playstation2

• Processors designed for computer entertainment
  must perform 3D graphics calculations, especially
  geometry and perspective transformations.
• The architecture is embodied in the
  PlayStation2s "Emotion Engine" CPU, which uses
  vector units (VUs) as the key units for
  floating-point calculations.

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Emotion Engine

• Geometry calculations transforms, translations,
  etc.
• Behavior/World simulation enemy AI, calculating
  the friction between two objects, calculating the
  height of a wave on a pond, etc.
• The Emotion Engine's job is to produce display
  lists (sequences of rendering commands) to send
  to the Graphics Synthesizer

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System Architecture of PS2
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The Emotion Engine(continued)
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The Emotion Engine(continued)
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Modes of operation for the VPU

• Macromode
• The FPU, and VU0 all form a logical
  and functional unit
• Micromode
• VPU no longer executes commands over the
  coprocessor-2 bus
• Instead, relies on 64-bit instructions

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The Emotion EngineVector Unit
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Emotion Engine

• 128 bits floating-point registers divided into
  four 32-bit fields
• Each of the FMACs can do the following
  instructions
• - Floating-Point Multiply-Accumulate (1
  cycle)
• - Min/Max (1 cycle)

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Emotion Engine

• x3 x0 x1 x2 (FMACx)
• y3 y0 y1 y2 (FMACy)
• z3 z0 z1 z2 (FMACz)
• w3 w0 w1 w2 (FMACw)
• Four multiplication and addition in one cycle

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PlayStation 3
The heart of the Sony PlayStation 3
The Cell Processor
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Cell
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Cell History

• IBM, SCEI/Sony, Toshiba Alliance formed in 2000
• Design Center opened in March 2001
• Based in Austin, Texas
• Single CellBE operational Spring 2004
• 2-way SMP operational Summer 2004
• February 7, 2005 First technical disclosures
• October 6, 2005 Mercury Announces Cell Blade
• November 9, 2005 Open Source SDK Simulator
  Published
• November 14, 2005 Mercury Announces Turismo Cell
  Offering
• February 8, 2006 IBM Announced Cell Blade

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Cell Broadband Engine (Cell)
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Cell Broadband Engine (Cell)
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Power Processor Element- PPE

• General purpose, 64-bit RISCprocessor (PowerPC
  AS 2.0.2)
• 2-Way hardware multithreaded
• L1 32KB I 32KB D
• L2 512KB
• Coherent load / store
• VMX-32
• Real time Controls
• Locking L2 Cache TLB
• Software / hardware managed TLB
• Bandwidth / Resource Reservation
• Mediated Interrupts

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Power Processor Element
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Power Processor Element
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Synergistic Processor Element- SPE

• Provides the computational performance
• Simple RISC User Mode Architecture
• Dual issue VMX-like
• Graphics SP-Float
• IEEE DP-Float
• Dedicated resources unified
• 128x128-bit RF, 256KB Local Store
• Dedicated DMA engine Up to
• 16 outstanding requests

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Synergistic Processor Element
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Synergistic Processor Element
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Memory Flow Control System
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Data Layout in Registers
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SPE ISA
204 instructions
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Instruction format
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I/O and Memory Interfaces

• I/O Provides wide bandwidth
• Dual XDRTM controller
• (25.6GB/s _at_ 3.2Gbps)
• Two configurable interfaces
• (76.8GB/s _at_6.4Gbps)
• Configurable number of Bytes
• Coherent or I/O Protection
• Allows for multiple system
• configurations

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Thank you