Low Energy FlipFlop Design

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Low Energy Flip-Flop Design

• Dejan Markovic
• Prof. Borivoje Nikolic
• Prof. Robert W. Brodersen
• Department of EECS
• University of California, Berkeley
• BWRC Retreat, January 2000

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Motivation

• Clock power dissipation (about 30 of the total
  system power) is divided between three major
  contributors
• Clock wires
• Clock buffers
• Flip-Flops
• Power consumed in Flip-Flops can be significantly
  reduced in some applications (DCT) by Flip-Flop
  selection Hamada et al., ISSCC 99
• Clock buffer design is tightly related to the
  design of Flip-Flops

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Conventional Flip-Flop Design

• Master Slave Latches
• Small clock-output delay, but positive setup time
• Clock generated locally, clock load is high
• Feedback added for static operation
• Pulse Triggered Latches
• First stage is pulse generator
• generates a pulse (glitch) on a rising edge of
  the clock
• Second stage is a latch
• captures the pulse generated in the first stage
• Pulse generation results in a negative setup time
• Frequently exhibit a soft edge property (negative
  setup time)
• Power is always consumed in the pulse generator!

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Low Energy Flip-Flop Design

• E ?? C ? VDD ? Vswing
• Energy reduction mechanisms
• Reduce node switching probability
• Reduce switched capacitance
• Scale down supply voltage
• Low swing circuit techniques
• Low Energy Flip-Flop Techniques
• Reduced Clock Swing
• Data Transition Lookahead (Clock-On-Demand)
• Activate internal clock only when the input data
  is to change the output
• Dual Edge Triggered

DL-DFF circuit from Nogawa et al., JSSC 05/98
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Performance Metrics

• Setup/Hold time f (CLK slope, VDD)
• Energy per transition
• Useful transitions are 01 and 10
• Explore 00 and 11 transitions too to see how much
  energy can be saved by
  deactivating internal clock
• TCLK-Q f (CLK slope, Setup/Hold times, VDD)

• Sum of setup time and CLK-Q delay is the only
  true measure of the performance with respect to
  the system speed
• T TCLK-Q TLogic Tsetup Tskew

TLogic
TClk-Q
TSetup
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Test Example Master Slave Latch

• PowerPC 603 (Gerosa, JSSC 12/94)

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Delay vs. Setup/Hold Times

• Setup time increases with increase in supply
  voltage
• Hold time decreases with increase in supply
  voltage
• Sampling window widens as supply voltage increases

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Energy vs. Setup/Hold Times
For this topology, decrease in energy vs. VDD is
better than quadratic, because some internal
nodes dont swing rail-to-rail
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Future Work

• Measure what is a minimum energy needed for a
  Flip-Flop to record one transition at its output,
  for a given input data throughput
• Find the minimum energy solution of the entire
  timing sub-system containing clock distribution
  network and timing elements
• Multiple voltage domains
• Flip-Flop selection for Power-Delay tradeoff
• Clock generation and clock distribution to
  multiple clock domains