Implementing Precise Interrupts in Pipelined Processors

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Implementing Precise Interrupts in Pipelined
Processors

James E. Smith Andrew R.Pleszkun Presented
By Shrikant G.
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Interrupt

• Interrupt Stop and resume.
• Precise interrupt
• Imprecise interrupt

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Types of interrupts

• Program Interrupts
• Referred sometimes as traps caused during
  fetching and execution of specific instructions.
• Exception, Instruction execution results in an
  error such as divide by zero, underflow or
  overflow.
• External Interrupts
• I/O device request, invoking a service from a
  user program
• Program has executed for a predetermined time,
  these interrupts usually implement time sharing.
• A fault in the hardware may cause all executing
  programs to abort.

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Historical Survey

• Precise interrupt problem is a very old one and
  do exist along with the first pipelined
  computers.
• Due to problems in implementation, precise
  interrupts were sacrificed in favor for maximum
  parallelism and design simplicity, although in
  these machines I/O interrupts were precise.

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Example code
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Interrupt in sequential model processors
pc5,R1,R2,R0,R5,R7
4 R1 ? (R2A)
pc6,R3,R1,R2,R0,R5,R7
5 R3 ? (R2B)
pc7,R4,R3,R1,R2,R0,R5,R7
Interrupt occurs XX
6 R4 ? R1fR3
Interrupt program running
110 R2 ? 44
1. Keep pc7,R4, R3,R1,R2,R0,R5,R7, 2. Program
suspended

150 R0 ? 100
Interrupt program stop
pc8,R4,R3,R1,R2,R0,R5,R7,
7 R0 ? R0R5
1. restore pc7,R4, R3,R1,R2,R0,R5,R7, 2.
Program resume
In sequential model processors, the interrupt is
precise. It guarantees suspended program can be
resumed.
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Interrupt in pipelined processors
pc5,R1,R2,R0,R5,R7
4 R1 ? (R2A)
pc6,R3,R1,R2,R0,R5,R7
5 R3 ? (R2B)
6 R4 ? R1fR3
Interrupt occurs XX
pc8,R3,R1,R2,R0,R5,R7,
7 R0 ? R0R5
Interrupt program running
110 R2 ? 44
1. Keep pc8,R3, R1, R2,R0,R5,R7 2. Program
suspended

Interrupt program stop
150 R0 ? 100
1. restore pc8,R3,R1, R2,R0,R5,R7 2. Program
resume
8 (R0C) ? R4
R4 isnt available
9 R2 ? R2 R5
In pipelined processors the interrupt could be
imprecise, It does not guarantee suspended
program can be resumed.
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Parallel pipeline implementation for a simple
architecture
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Precise Interrupt Methods in pipelined processors

• In-Order Instruction Completion
• Reorder Buffer with Bypass paths
• History Buffer
• Future File

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In-Order Instruction Completion

• Instructions modify the process state only when
  all previously issued instructions are known to
  be free of exception conditions.

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In-Order Instruction Completion- result shift
register
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In-Order Instruction Completion- result shift
register
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In-Order Instruction Completion- process state
modification

• Registers
• Main memory
• Program Counter

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out-of-order instruction completion methods

• Limitation of in-order completion
• Fast instructions may sometimes get held up even
  if there is no dependency.
• Further block other instructions.
• 6. R4 ? R1 fR3 Floating add 6 clock periods
• 7. R0 ? R0 R5 Inc. loop count 2 clock periods
• Methods to allow out-of-order completion.
• Basic reorder buffer, Reorder buffer with bypass
  paths.
• History buffer, future file.

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Basic reorder buffer method Organization.

• Reorder buffer
• Separate the process of completing instructions
  from instruction commit
• out-of-order completion.
• In-order commit.
• Reorder buffer is used to rearrange instructions
  before they commit.

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Basic reorder buffer method Structure.

• Result shift register
• TAG field will guide result and exception
  conditions to reorder buffer.
• Reorder buffer
• Tail when an instruction issues, create one
  entry.
• Head when it contains valid result, check and
  remove.
• Example
• Two instructions relative positions in the two
  buffers.

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Basic reorder buffer Keep precise process state

• Keep register value precise
• No exception at the head results are written to
  register file.
• Exception at the head issue is stopped to
  process interrupt and no further writes to
  register file.
• Keep memory precise
• Hold stores in the issue register until all
  previous instructions are known to be free of
  exceptions.
• Stores are issued. An dummy entry is put to
  reorder buffer.
• Keep program counter precise
• Program counter is stored in one field of reorder
  buffer as instructions are issued.

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Reorder buffer with bypass paths

• Limitation of basic reorder buffer.
• Operands are held in reorder buffer.
• Instructions dependent on operands can not be
  issued.
• Reorder buffer with bypass paths is proposed.
• Bypass paths are provided from reorder buffer to
  register file output latches.

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Reorder buffer with bypass paths precise process
state.

• Keep precise register
• Operands are not actually written to register
  file but to register file output latches.
• Register will not be modified until the
  instruction reaches the head of reorder buffer.
• Keep precise memory and PC
• Same as before

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Methods to reduce bypass circuit.

• Limitation of reorder buffer with bypass paths
• The number of bypass comparators and the amount
  of circuitry for multiple bypass check.
• History buffer, future file are proposed.
• Basic idea place computed results in a working
  register file, but retain enough state
  information so a precise state can be restored.

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History buffer organization

• History buffer
• Instruction issues The current value of the
  destination register is stored to history buffer
  entry.
• Instruction completes Results on the result bus
  are written directly into register file.

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History buffer Keep precise process state

• Keep register precise
• Tag field is used to guide exception to history
  buffer.
• Old values are kept when instruction issue.
• No exception head is removed.
• Keep memory and PC precise
• Same as before
• Example
• Old value in entry 4, 5.

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Future file

• Similar to the history buffer method.
• Keep register precisetwo register files.
• Architecture file
• Future file
• Keep memory and PC precise.
• Same as before.

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Performance evaluation

• Environment
• CRAY-1S simulation system.
• The first 14 Lawrence Livermore loops are used
  as simulation workload.
• Five methods are classified as three groups
• In-order completion.
• Simple reorder buffer
• Reorder buffer with bypass, history buffer,
  future file.
• Two evaluation cases based on different methods
  to handle store.

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Performance evaluation(1)

• Measure condition
• store blocked until the results pipeline is
  empty.
• In-order completion is independent on the number
  of entries.
• In-order completion is better if buffer is small.
• If the number of entries increases beyond 3 ,the
  other two are better.

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Performance evaluation(2)

• Measure condition
• Stores are issued and held in the memory
  pipeline.
• Second method to handle store offers a clear
  improvement over first method.
• Performance degradation for eight-entry reorder
  buffer with bypass paths is only 3 percent.

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Indication from the methods.

• If the entries in the reorder buffer exceed a
  certain value, the performance will not be
  improved.
• In both of the two tables, the number is eight.
• Tradeoff between performance degradation and cost
  of implementing a method.

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Outline

• Extensions
• Architectural Solutions
• Summary

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Extensions

• Additional state information
• Virtual memory
• Cache memory

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Other State Values

• State register
• Condition codes

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Virtual Memory

• Load/store instructions pass through the address
  translation section in order
• reserve time slots in the result pipeline and/or
  reorder buffer
• If addressing fault, the instruction and all
  subsequent load/store are cancelled

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Virtual Memory Using ROB

• Send the page fault to reorder buffer.
• Guide load/store to the correct reorder buffer
  using tag.
• Entry removed while reaching the head.
• Exception causes all further entries discarded.

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Cache Memory

• Store-Through cache
• Write-Back cache

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Vectors Implementation

• Two classes of vector registers.
• Those with vector registers
• Instruction finishes producing results before
  next begins.
• Memory-Memory vector operations.

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Architectural Solutions

• Freeze and dump
• Save program counters
• Save a sequence of instructions

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Summary

• In-order instruction completion
• Reorder buffer
• Bypass paths, History buffer and Future file
• Extensions
• Architecture solutions