Group3: No more counting of Literals

1
Group3 No more counting of Literals

• Subramanian Iyer
• Satrajit Chatterjee
• Ajit Pal
• Yinghua Li
• Pawel Kerntopf
• Donald Chai
• Dennis Wu
• Leyla Nazhandali
• Ingmar Neumann
• Babette Van Antwerpen
• Alan Mishchenko

• Michael Theobald
• Victor Kravetz
• Yunjian Jiang
• Aiqun Cao
• Jordi Cortadella
• Jackie Rice
• Jean-Christoph Madre
• Timothy Kam
• Christian Stangier
• Charles Brej
• Dmitri Maslov

2
When/Why We Count Literals

• Multi-level combinational logic optimization
• LC is sum of literals of all nodes in network
• Different flavours of LCs
• Delay independent logic factorization
• Dont care optimization
• Objective is to minimize LC
• Used to correlate well with circuit area

3
Problems

• Factorization can have negative effects on
• Delay
• Creates additional levels of logic, higher
  fanouts
• Area
• Can result in larger area after technology
  mapping (e.g. tree based mapper)
• Can increase congestion, wire length
• Power
• Logic duplication can reduce power

4
Problems (contd.)

• No correlation between LC and area, delay and
  power.
• Logic optimization happens quite late in
  synthesis process
• Earlier optimizations may create problems that
  cannot be fixed at this stage
• Blame the other guy!

5
Directions

• 1. Identify cost vectors that correlate with
  objective functions
• Should capture
• Structural regularities
• Local communications
• Wire length, congestion
• Efficient to compute
• Need access to real circuits
• 2. Develop algorithms