Verilog-A is for Equation Specification, not for Modeling

1
Verilog-A is for Equation Specification, not for
Modeling
Colin McAndrew Freescale Semiconductor
Laurent Lemaitre Freescale Semiconductor
Zoltan Huszka Austriamicrosystems
Geoffrey Coram Analog Devices

• MOS-AK Meeting
• Saturday December 13, 2008

2
Overview

• A Brief History of Verilog-A for Compact Modeling
• A Brief Review of How Circuit Simulators Work
• How to Leverage Understanding of How Simulators
  Work to Implement Desired Equations
• thinking outside the equivalent network
  modeling box
• example 1 BJT excess phase
• example 2 single formulation resistor that can
  handle R0
• Summary

3
What is Verilog-A?

• Initially (mid to late 1990s), a language for
  analog behavioral modeling to enable
• top down AMS design at the block level
• efficient top-level AMS verification
• VHDL-AMS is a competing language developed
  around the same time for the same purposes
• So how does Verilog-A relate to compact modeling?

4
Automation in Compact Modeling

• In the late 1980s automation began to creep into
  the development of simulators
• especially for the time-consuming and error-prone
  task of implementing compact models (symbolic
  derivative generation)
• added impetus to the on-going migration from
  diffused model code to modular model code
• Simulator-model interfaces of the 1980s and
  1990s
• WATAND
• Saber/MAST major commercial success
• Tektronix (very early pioneer)
• ADMIT plus various compilers (ATT)
• iSMILE
• CMC Type-II interface (DOA circa 1995
  engineering ? CS)

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The Problem
The Solution
Common Language/Interface
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Automated Model Implementation

• Mostly flopped in mid 1990s
• VBIC was the first public model defined in high
  level code
• generated FORTRAN and C also provided
• these were used
• high-level pseudo-code was not! (except by
  Tektronix)
• chasm between engineers and advanced software
  techniques
• Many misconceptions
• code is slow compared to hand-coded C
• within 10 of hand coded and getting better
• will be faster one day (proven already), then
  works for all models!
• cannot use for parameter extraction
• if its in a simulator its in your
  simulator-based extractor!
• different code for different simulators will give
  different results
• different compile flags on the same platform give
  different results!

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Enter Verilog-A

• Significant issue with the concept (high-level
  language compilers) was the lack of a standard
  high-level language!
• Verilog-A was obviously the solution for this
• VHDL-AMS touted as well initially
• Minor deficiencies overcome by compact model
  additions defined in LRM2.2
• CMC accepted models defined in Verilog-A circa
  2004
• Verilog-A has become the de facto standard
  language for defining compact models

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Moving Beyond Models

• You can use Verilog-A to define physical
  compact models
• But this can be very restrictive
• constrained to think in terms of equivalent
  networks
• constrained to think in terms of I(V), Q(V)
  relations
• A circuit simulator is an equation solver
• Think of what equations you want to force the
  simulator to solve, then develop Verilog-A
  constructs to force this
• not thinking in terms of physical representation

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How SPICE Works Simple BJT Model and Circuit
Ibc
c
Qbc
Icc
RB
x
b
Vc
Ibe
Qbe
Ib
e
RE
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System Equations (DC) MNA

• Unknowns are V(x), V(b), V(c), V(e), and IcI(Vc)

x
b
e
c

• VbeV(b)V(e) and VbcV(b) V(c)

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Branch Jacobian Entry (Element Matrix Stamp)

• Solve KCL SI (V)f(V)0 at each node, plus the
  voltage equation for voltage sources (and
  inductors)
• nonlinear, so need iterative Newton solution
• Vk1VkdVk, JkdVk-f(Vk), Jk ?I/?V VVk
• Easy to set up Jacobian Jk in an algorithmic
  fashion
• rows are defined by nodes that the current flows
  between
• ve for flow into node, ve for flow out-of node
• columns are defined by the branch control
  voltages
• ve for first node, ve for second, for VabV
  (a)-V (b)
• voltage sources and inductors add a row for the
  voltage equation and a column (unknown system
  variable) for the current

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Jacobian Assembly (Stamping)

• gce?Icc/Vbe, gcc?Icc/Vbc, gm gce gcc , go -
  gcc

• gbe?Ibe/Vbe

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SPICE

• Circuit simulators are not really circuit
  simulators
• for DC they are multidimensional nonlinear
  equation solvers
• for transient they are nonlinear ordinary
  differential equation (ODE) solvers
• multidimensional nonlinear equation solvers at
  each time point
• Instead of thinking of Verilog-A as a means to
  define equivalent network models, think of it as
  a means of specifying equations for numerical
  solution
• formulate the equations you want
• understand how MNA equations are set up
• work out how to use Verilog-A to set up the
  desired equations

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Weil-McNamee Excess Phase for BJTs

• Goal implement a phase shift for gm with the
  least possible change in the magnitude of gm
• network approach leads to 2nd order Bessel
  (linear phase) filter
• straight forward to implement as RLC circuit (L.
  Wagner, IBM)

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How Can We Get Rid of the Pesky Inductor?
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Can We Better Approximate an Ideal Phase Shift?

• Only 1 added system variable!

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Phase Response
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Magnitude Response
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What about Resistors?
p
m
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The Solution ... sort of

• For reasonable R
• natural for NA (SPICE)
• efficient for NA
• nasty for R0 or small R
• For small R
• extra MNA system variable
• no worries for R0 or small R

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The ... sort of Solution
include "disciplines.h" define rm 0.001 module
r_va(p,m) inout p,m electrical
p,m parameter real R 1.0 from0.0inf) analog
begin analogBlock if (Rltrm) V(p,m) lt
I(p,m)R else I(p,m) lt V(p,m)/R end //
analogBlock endmodule
EASY TO DEFINE ? HARD TO IMPLEMENT ?
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Why ... sort of is not Enough

• Does work in Verilog-A
• excellent feature of the language
• Does not (easily) work for
• built-in model implementation via ADMS
• some model interfaces for some simulators
• dynamic switching for the case when R varies with
  bias
• Do not want to switch formulations during
  iterative solution
• dynamically adds extra system variable I(p,m)
• Observation must have this current for VRI
  formulation
• Conclusion explicitly include in model
  formulation

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How do We Force Verilog-A to do What We Want?

• For simplicity of implementation in model
  interfaces, need to get rid of voltage
  contribution
• only want strict nodal analysis formulation
• How can we do this for R0?
• Want V(p,m)0
• Set up currentcontribution forthis as the only
  flowinto a node
• Forces set up ofequation we want!

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The R0 Solution
include "disciplines.h" module
r_va(p,m) inout p,m electrical
p,m,I_r parameter real R 1.0
from0.0inf) analog begin analogBlock
I(I_r) lt V(p,m) I(p,m) lt 1.0e-6V(I_r) end
// analogBlock endmodule
second equation forces V(I_r) to be current
flowing between p and m
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Extension for Small Nonzero R
include "disciplines.h" module
r_va(p,m) inout p,m electrical
p,m,I_r parameter real R 1.0
from0.0inf) analog begin analogBlock
I(I_r) lt V(p,m)-1.0e-6RV(I_r) I(p,m) lt
1.0e-6V(I_r) end // analogBlock endmodule
first equation forces V(p,m)IR (voltage on node
I_r is current p?m)
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Final Result
include "disciplines.h" define rm 0.001 module
r_va(p,m) inout p,m electrical
p,m,I_r parameter real R 1.0
from0.0inf) analog begin analogBlock
I(I_r) lt V(p,m)-1.0e-6RV(I_r) if (Rltrm)
I(p,m) lt 1.0e-6V(I_r) else I(p,m) lt
V(p,m)/R // IGV formulation end //
analogBlock endmodule
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Final Model

• Manipulated Verilog-A equations we want to solve
• Resistor model that does not switch formulations
  from current contribution to voltage contribution
• strictly nodal formulation
• easy to implement in all simulator model
  interfaces
• numerically well behaved for all R0
• can be adapted to use same switch for voltage
  variable R
• direct bias dependence
• indirect bias dependence (e.g. self-heating)
• Cost is added system variable V(I_r) is added for
  all values of R, not just Rltrm

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Summary

• Circuit simulators are equation, not circuit,
  solvers
• Historical modeling approach of equivalent
  networks and a physical approach may not always
  give desired result
• By thinking about what equations you want to
  implement or solve, and understanding how MNA is
  set up, you can use Verilog-A to implement
  non-obvious but useful models
• Note if currents are mapped to node voltages
  (i.e. system variables), they need to be scaled
  by the voltage/current tolerance ratio (default
  is 1.0e6)