Mic1: Microarchitecture

1
Mic-1 Microarchitecture

• University of Fribourg, Switzerland
• System I Introduction to
• Computer Architecture
• WS 2005-2006
• 18. January 2006
• amos.brocco_at_unifr.ch

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Mic-1 Microarchitecture (1)

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Mic-1 Microarchitecture (2)
Data path Control section
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The data path

• 32-bit registers(with exception of PC and MDR,
  which are 8 bit registers)
• B bus to drive data to the ALU
• C bus to drive data from the ALU to registers
• H register as A-input of the ALU
• ALU with 6 control signals (and 2 outputs, N to
  test for Negative numbers and Z to test for Zero)

From/ To Memory
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ALU Control Signals

1
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The data path
Registers have control signals to enable/disable
reading from them (put value on the B bus) and
writing to them (store value from the C bus) It
is possible to read only from one register at
time so we can use a 4 -gt 16 bit decoder It is
possible to write to one or more registers at the
same time so we need 9 control signals for the C
bus.
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Data path synchronization (1)

• Control signals stabilize
• A register value is put on the B bus
• ALU and shifter operate
• Result propagate on the C bus
• Result is written in the registers on the raising
  edge of the next clock pulse

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Data path synchronization (2)

• Control signals stabilize
• Register's value is put on the B bus
• ALU and shifter operate
• Result propagate on the C bus
• Result is written in the registers on the raising
  edge of the next clock pulse

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Data path synchronization (3)

• Control signals stabilize
• Register's value is put on the B bus
• ALU and shifter operate
• Result propagate on the C bus
• Result is written in the registers on the raising
  edge of the next clock pulse

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Data path synchronization (4)

• Control signals stabilize
• Register's value is put on the B bus
• ALU and shifter operate
• Result propagate on the C bus
• Result is written in the registers on the raising
  edge of the next clock pulse

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Data path synchronization (4)

• Control signals stabilize
• Register's value is put on the B bus
• ALU and shifter operate
• Result propagate on the C bus
• Result is written in the registers on the raising
  edge of the next clock pulse

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MAR and MDR (1)
32 bit registers connected to the main
memory MAR Memory Address Register MDR
Memory Data Register MAR has only one control
signal (input from C) Two memory operations
read and write
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MAR and MDR (2)
Data is word (48bit 32bit in our ISA)
addressed! gtMAR addresses are shifted 2bit left
( 4)
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Memory Access
A memory read initiated at cycle k delivers data
that can be used only in cycle k2 or
later!

• MAR is loaded
• Memory access
• MDR is loaded with data read from memory
• Data in MDR is available

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Memory Access
A memory read initiated at cycle k delivers data
that can be used only in cycle k2 or
later!

• MAR is loaded
• Memory access
• MDR is loaded with data read from memory
• Data in MDR is available

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Memory Access
A memory read initiated at cycle k delivers data
that can be used only in cycle k2 or
later!

• MAR is loaded
• Memory access
• MDR is loaded with data read from memory
• Data in MDR is available

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Memory Access
A memory read initiated at cycle k delivers data
that can be used only in cycle k2 or
later!

• MAR is loaded
• Memory access
• MDR is loaded with data read from memory
• Data in MDR is available

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Memory Access
A memory read initiated at cycle k delivers data
that can be used only in cycle k2 or
later!
lt clock cycle 3 gt

• MAR is loaded
• Memory access
• MDR is loaded with data read from memory
• Data in MDR is available

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Memory Access (2)
Until start of cycle k2 the MDR register
contains old data It is possible to issue
consecutive requests, for example at time k and
k1 corresponding results will be available at
k2 and k3
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PC and MBR
8 bit registers connected to the main memory
used to read (fetch) ISA instructions PC
Program Counter MBR Memory Buffer
Register Access also requires one clock cycle (k
-gt k2) MBR has two control signals for the B
bus, for signed or unsigned operations One
memory operation fetch
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H register
Is the A-input of the ALU Has only one
control signal output to the ALU is always
enabled
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ISA, IJVM, Microarchitecture
ISA Instruction Set Architecture (defines
instructions, memory model, available
registers,...) IJVM An example ISA (it's stack
based architecture) The IJVM (Integer Java
Virtual Machine) level executes the IJVM
Instruction set The IJVM is (in this case)
implemented by the Mic-1 Microarchitecture
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Mic-1 implementation
The Mic-1 is a microprogrammed architecture
each IJVM instruction (Macroinstruction) is
divided one or more steps. In each step, a
microinstruction is executed by the
Mic-1. Microinstructions are simpler than ISA
macroinstructions.
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Control section
MicroProgram Counter (MPC)
Control store holding microinstructions

MicroInstruction Register (MIR) containing
current microinstruction
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Microinstructions
36bit wide microinstructions Microinstructions
are executed in the control section (a CPU in
the CPU) Microinstructions basically drive
control signals for the data path. To avoid the
need for a real (micro)Program Counter each
microinstruction specifies the address of the
following one. Microinstruction addresses are
9-bit wide
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Microinstruction format (1)

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Microinstruction format (2)

Addr Address of the next microinstruction
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Microinstruction format (3)

JAM Determines how to choose next
microinstruction
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Microinstruction format (4)

ALU Control signals to choose ALU operations
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Microinstruction format (5)

C Enables writing from C bus to the selected
registers
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Microinstruction format (6)

Mem Controls memory read/write/fetch operations
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Microinstruction format (7)

B Controls which register can write to the B bus
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Driving control signals

• MIR is loaded on the falling edge of the clock
  based on the MPC address, control signals
  propagate
• ALU Operation N and Z values available and saved

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Driving control signals

• MIR is loaded on the falling edge of the clock
  based on the MPC address, control signals
  propagate
• ALU Operation N and Z values available and saved

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Driving control signals

• MIR is loaded on the falling edge of the clock
  based on the MPC address, control signals
  propagate
• ALU Operation N and Z values available and saved

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Next microinstruction (1)
Addr (the address of the next microinstruction
coded in the current microinstruction) is copied
in the MPC (lower 8 bits, high bit is 0) If J is
000 the next address is in the MPC and the next
microinstruction can be read from the control
store (Note microinstruction are not stored in
the same order as Figure 4-17) If J is not 000
it is necessary to compute the next microaddress
depending on the values of J, N and Z (whose
value has been saved in flip-flop because the ALU
returns correct result as long as data is passing
through it)
Addr8
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Next microinstruction (2)
If JAMN or JAMZ are set to 1, the 'High bit'
function computes the value of the high bit of
the MPC as follows F (JAMZ and Z) or (JAMN
and N) or Addr8 (To avoid confusion Addr8
is in fact the 9th bit, the highest, of Addr, as
bits count start from 0) So the MPC can assume
either the value of Addr or the value of Addr
with the high bit ORred with 1
Addr8
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Next microinstruction (3)
F (JAMZ and Z) or (JAMN and N) or Addr8 An
example Let Addr lt 0xFF (or we would get the
same value, 0xFF in either case) Let JAMZ 1
(or JAMN 1) Let Z1 (or N1) in this case
MPC is Addr 0x100 (for example if Addr0x92,
MPC 0x92 0x100 0x192) Note 0x100 256
Addr8
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Microinstructions (4)
...but why is all that stuff required to
determine the next microinstruction ? Reason
efficiency In case of conditional jumps
(if..then..else) we normally need two jump
addresses as parameter. To uniform the
microinstruction format we want all instruction
to have the same length either we make all
microinstruction contain two addresses (-gt waste
of space) or (better solution) we specify only
one address and compute the second one as Addr
Constant Value (in Mic-1 Constant Value 0x100)
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Next microinstruction (5)
If JMPC 0, Addr is copied to MPC If JMPC 1,
an the lower 8-bits of Addr are ORred with the
MBR value, and the result is put in the
MPC Normally when JMPC 1, Addr is set to
either 0x000 or 0x100 JMPC is used to jump to
the address specified by the MBR, which, as we
will see, contains the opcode of the ISA
instruction in fact, microinstruction for each
macroinstruction are stored starting from the
position determined by the opcode of the latter.
Addr8
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Next microinstruction (6)
Example ISA instruction BIPUSH opcode is
0x10 corresponding microinstructions starts at
address 0x10 in the control store For the
reasons explained in the previous slides, it is
clear that the next microinstruction can be
determined only when the MBR, N and Z are ready,
i.e. starting from the successive clock pulse)
Addr8
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Procedure calls
The fact all programming language support the
concept of procedures (methods). Each method has
its own local variables that are no more
accessible when the procedure has returned. The
problem Where should these variables be kept in
memory?
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Solutions
Solution 1 Give each variable its own memory
address but what if the procedures calls
itself? Solution 2 Use a data structure called
execution stack
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Execution stack (1)
The execution stack is stored in an area of
memory It is reserved for storing variables It
is possible to push values on the top of the
stack or pop values from the top A special
register (SP Stack Pointer) always contains the
address of the top of the stack
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Execution stacks (2)
How a stack solves the problem of procedure call
? A special register (LV) stores the base
absolute address (position) in the stack from
where local variables of the current procedure
are stored. Local variables are referred by mean
of a relative distance (offset) from the absolute
address pointed by LV. The data structure between
LV and SP is called local variable frame of the
current procedure.
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Example (1)
A procedure 'A', which has local variables a1,a2
and a3 is executing a1 is at address LV,
a2 is at LV1, a3 is at LV2
Memory
Execution stack
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Example (2)
'A' calls procedure 'B', which has local
variables b1, b2, b3, b4 'B' local
variables are pushed on the stack. LV is updated
to point to the address where 'B' local variables
start.
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Example (3)
'B' calls procedure 'C', which has local
variables c1 and c2
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Example (4)
'A' calls procedure 'D', which has local
variables d1, d2, d3, d4 and d5, which are stored
at the same location of the not still available
'B' and 'C' local variables
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Stack based machine
IJVM is a stack based machine The stack is also
used to store operands during the computation of
arithmetic expressions as well as the result
such use is called operand stack Beside access
to the main memory, the IJVM only exposes the
stack structure to the programmer (no registers
are available and in any way directly accessible
with the IJVM instruction set)
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Operand stack (1)
Let a1, a2 and a3 be local variables representing
integer numbers How to compute a1 a2 a3 on a
stack based architecture? Note We suppose to
have an instruction that sums the two values on
the top of the stack, and pushes the result back
on the stack
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Operand stack (2)
First values of a2 and a3 are pushed on the
stack
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Operand stack (3)
Then we execute the instruction for the sum it
will pop the two top-most values on the stack,
compute their sum and push the result back on the
stack.
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Operand stack (4)
Finally we save back the value at the top of the
stack in a1
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Memory organization
CPP, LV and SP points to 4-byte words, PC points
to a byte

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IJVM ISA (1)
20 Instructions Integer Arithmetic Instruction
are composed of an operation code (opcode) and an
optional operand (a memory offset or a constant)
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IJVM ISA (2)

• Types of instruction
• Push a word on stack (LDC_W, ILOAD, BIPUSH)
• Pop a word from the stack, assign its value to a
  local variable (POP, ISTORE)
• Arithmetic (integer) and logic operations
  (IADD,ISUB,IAND,IOR)
• Conditional Branching, Jumps (IFEQ, IFLT,
  IF_ICMPEQ, GOTO)
• Swapping of values on top of the stack (SWAP)
• Duplicate value on top of the stack (DUP)
• Format conversion (prefix instruction WIDE)
• Method/Procedure call (INVOKEVIRTUAL)
• Return from a method (IRETURN)
• NOP
• Adding a constant to a local variable (INCC)

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IJVM ISA (3)
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Example Program
Java Java assembly IJVM program
Instructions are replaced by Hex opcodes
Instructions are replaced by Hex opcodes
Local variables are stored on the stack and
referenced by mean of an offset starting from the
LV pointer
Labels in the assembly code are replaced by
effective offsets in the IJVM code (0x0F 15)
F
Operand Stack evolution during execution
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INVOKEVIRTUAL
INVOKEVIRTUAL is used to call another
method. This instruction allocates the space for
the reference of the object (OBJREF) to be
called, for the parameters and local variables
(Parameter 1, 2, and 3), for the return address
(INVOKEVIRTUAL's following instruction) e a
pointer to the Caller's LV (pointer to the
previous local variable frame) Finally it changes
the value of the PC register so that it points to
the code of the called method.
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INVOKEVIRTUAL Example (1)
.main ... LDC_W objref BIPUSH -1 BIPUSH
-10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ
EQ ... EQ HALT .end-main

• The program calls the cmp(p1,p2) method, which
  accepts two parameters, compares them and
  returns
• -1 if p1 lt p2
• 0 if p1 p2
• 1 if p1 gt p2
• The method is called with p1 -1 and p2 -10
  we expect that it returns 1.

SP
...
LV
Stack before INVOKEVIRTUAL, current procedure is
main
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INVOKEVIRTUAL Example (2)
.main ... LDC_W objref BIPUSH -1 BIPUSH
-10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ
EQ ... EQ HALT .end-main
objref is a reference to the method stored in the
constant pool it's use is related to the way the
Java Virtual Machine operates, but it is not
really necessary in our IJVM
SP
objref
...
LV
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INVOKEVIRTUAL Example (3)
.main ... LDC_W objref BIPUSH -1 BIPUSH
-10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ
EQ ... EQ HALT .end-main
The first parameter is pushed on the stack p1
-1
SP
-1
objref
...
LV
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INVOKEVIRTUAL Example (4)
.main ... LDC_W objref BIPUSH -1 BIPUSH
-10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ
EQ ... EQ HALT .end-main
The second parameter is pushed on the stack p2
-10
SP
-10
-1
objref
...
LV
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INVOKEVIRTUAL Example (5)
.main ... LDC_W objref BIPUSH -1 BIPUSH
-10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ
EQ ... EQ HALT .end-main
The method cmp(-1, -10) is invoked
SP
-10
-1
objref
...
LV
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INVOKEVIRTUAL Example (6)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
Before executing the method, some operation must
be done allocate space for and assign values to
local variables (temp), save the address of the
instruction following the method call (return
address) and the LV register (base pointer of the
local variable frame of the caller), objref is
overwritten with a pointer to address of the
return address in the stack. LV is then updated
to the current local variable frame start.
SP
LV
return address
temp
caller's LV (in this case main's LV)
-10
-1
LV
link
address of the instruction that follows
INVOKEVIRTUAL
...
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INVOKEVIRTUAL Example (7)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
The value of the first parameter is loaded on the
stack p1 -1
SP
-1
LV
return address
temp
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (8)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
The value of the second parameter is loaded on
the stack p2 -10
SP
-10
-1
LV
return address
temp
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (9)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
Compute the difference (ISUB) between the two
values on top of the stack. Push the result back
on the stack.
SP
9
LV
return address
temp
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (10)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
Save the value on top of the stack in the temp
variable. Note This pulls the top-most value
off the stack, so after we need to re-push it.
9
SP
LV
return address
temp 9
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (11)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
Load the value of temp on the stack
SP
9
LV
return address
temp 9
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (12)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
If the value at the top of the stack is negative
(less than 0) jump to 'lt', else continue. The
value on top is popped. In this case 9 gt 0 we
continue...
9
SP
LV
return address
temp 9
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (13)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
temp is loaded back on the stack
SP
9
LV
return address
temp 9
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (14)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
If the top of the stack is equal to zero jump to
'eq', else continue As we have 9 we continue...
9
SP
LV
return address
temp 9
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (14)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
The constant value 1 is pushed on the stack (this
will be the return value of the cmp method)
SP
1
LV
return address
temp 9
-10
-1
LV
link
...
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INVOKEVIRTUAL Example (15)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
We jump to 'done'. On top of the stack the
return value 1 remains
SP
1
LV
return address
temp 9
-10
-1
LV
link
...
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IRETURN
IRETURN is used exit a method and return to the
caller This instruction deallocates the stack
space reserved for the INVOKEVIRTUAL call,
restores the values of the LV and PC registers
and assures that the return value is on top of
the stack.
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IRETURN Example (16)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
We return to the caller...
SP
1
LV
return address
temp 9
-10
-1
LV
link
...
ltComputer Architecture WS 2005-2006, 18 January
2006gt (78)
79
IRETURN Example (17)
.method cmp(p1,p2) .var temp .end-var ILOAD
p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT
lt ILOAD temp IFEQ eq gt BIPUSH 1 GOTO
done lt BIPUSH -1 GOTO done eq BIPUSH
0 done IRETURN .end-method
Values of the LV and SP registers are restored,
the top of the stack contains the return value of
the method, PC is restored to the saved value
(return address) so that execution continues from
the instruction following the INVOKEVIRTUAL call.
1
LV
return address
temp 9
-10
-1
SP
1
...
LV
ltComputer Architecture WS 2005-2006, 18 January
2006gt (79)
80
IRETURN Example (18)
.main ... LDC_W objref BIPUSH -1 BIPUSH
-10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ
EQ ... EQ HALT .end-main
We push the constant 1 on the top of the stack
SP
1
1
...
LV
ltComputer Architecture WS 2005-2006, 18 January
2006gt (80)
81
IRETURN Example (19)
.main ... LDC_W objref BIPUSH -1 BIPUSH
-10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ
EQ ... EQ HALT .end-main
We compare the two top-most values on the stack.
If they are equal (that's the case in this
example) jump to 'EQ'.
1
1
SP
...
LV
ltComputer Architecture WS 2005-2006, 18 January
2006gt (81)