Recap

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Recap
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Instruction Set Architecture

• There are 4 classes of ISA
• Stack
• Embedded processors
• Accumulator
• Embedded processors
• Register-memory
• Pentium
• Register-Register (Load-store)
• Sparc

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Instruction Set Architecture

• For a general purpose high-performance computer
• Register-Register (Load-store) is the preferred
  choice
• CPI uniform for most instructions
• Better pipelining
• Fixed length instructions
• Simpler encoding
• The complier is more complicated

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Important issues to consider for designing an ISA

• How to address and store objects (e.g.,
  instructions) in memory
• What are the different addressing modes that
  should be used
• What is the length of instructions
• What are the different instructions used
• What is the type and size of operands

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Addressing ? How a multiple byte data word stored
in memory

• Big Endian
• Most significant byte of a multi-byte word is
  stored at the lowest memory address
• e.g. Sun Sparc, PowerPC
• Little Endian
• Least significant byte of a multi-byte word is
  stored at the lowest memory address
• e.g. Intel x86
• Some embedded DSP processors would support both
  for interoperability

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Byte Ordering Examples

• Store 87654321 at address 0x0000, byte-addressable

Lower Memory Address
Lower Memory Address
87
21
0x0000
0x0000
65
43
0x0001
0x0001
43
65
0x0002
0x0002
21
87
0x0003
0x0003
Higher Memory Address
Higher Memory Address
BIG ENDIAN
LITTLE ENDIAN
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Memory Alignment

• Most processor registers are each 32 bits wide (1
  word).
• Memory is organized in to 8-bit bytes.
• In most processor architectures, words must start
  at addresses that are a multiple of 4.
• alignment restriction.
• on 64 bit architectures, words are 8-byte aligned

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Memory as Words
01001000 11010100 01111001 11010001 11010111
01011010 10000100 00001000 01001010 11001010
01000111 01000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000100
01001000 11010100 01111001 11010001
20 16 12 8 4 0
Address
Data
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Word alignment Words are aligned in memory if
they begin at a byte address that is a multiple
of the number of bytes in a word

Example If a word consists of 4 bytes, then
Aligned word
Mis-Aligned word
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Memory Alignment

• Alignment require that objects fall on address
  that is multiple of their size.

0
1
2
3
4
5
6
7
4
Word-aligned word at byte address 4.
2
Halfword-aligned word at byte address 2.
1
Byte-aligned (non-aligned) word, at byte address
1.
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Addressing Modes
12
85
75
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Addressing Modes

• Register (direct) mode

op opcode rs first source register rt second
source register rd destination register
Example ADD r1, r2, r3
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Addressing Modes

• Immediate mode

op opcode rs source register rt destination
register immed constant
Example ADDI r3, r1, 12
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Addressing Modes

• Displacement mode

Example LOAD r1, 100(r2)
r2 150 100(r2) 88
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Displacement and Immediate Values

• Important addressing modes Register, immediate,
  displacement, register indirect. Account for 88
  of workload.
• Through measurements, 12-16 bits are enough to
  cover the majority of cases for the value of
  immediate
• This will allow to have instruction sets of fixed
  size of 32 bits most microprocessors

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What about the new trend of 64-bit processors

• Intel Itanium
• AMD Hammer
• Alpha, SPARC, MIPS, and POWER
• All this new generation of microprocessors are
  64-bit microprocessors
• Does it mean that the instruction length has to
  be 64 bits? Not quite

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What about the new trend of 64-bit processors

• First, 64-bit microprocessor does NOT directly
  mean the instructions have to be 64 bits (but can
  easily handle that) for example the size of
  instruction for ITANIUM is 41 bits
• It means that the processor can get 64-bits of
  information (data or instructions) from the
  memory in one just one transfer
• It also means that the size of the registers are
  64 bits

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Is 64-bit processor more powerful than 32-bit
processor?

• May be yes may be NOT
• Pentium 4 (32 bits) is more powerful than Itanium
  (64 bits) in many applications
• It depends on so many other factors
• Pipelining efficiency
• ILP
• Cache
• Etc.