Camera Auto Focus

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Camera Auto Focus

• Presentation 4, February 14th, 2007

Team W1 Tom Goff (W11) David Hwang (W12) Kate
Killfoile (W13) Greg Look (W14) Design Manager
Bowei Gai Project Goal Design a low-power, small
auto focus chip for a camera or other
hand-held device
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Status

• Last Time
• C implementation
• Attempt at floor plan
• This Week
• Structural Verilog completed
• Major architecture revision
• Revised floor plan
• In Process
• Power control logic implementation
• Low-power component selection
• Unfinished
• Schematic
• Layout
• Extraction, LVS, post-layout simulation

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Big Picture Recap
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Design Decisions

• Optimization of rules
• Reduction of registers, additional preprocessing
  unit

• Led to a huge change in architecture

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Remember this?
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New Architecture
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AG Preprocessor
Zoom Out
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Delta I Preprocessor
Zoom Out
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Rule Logic
Zoom Out
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Transistor Count
Optimizes down from 25,230!
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Floor Plan
Dimensions 238 x 266
Lets make sense of all the wires and modules
here
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Floor Plan
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Testing of Components
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Structural Verilog

• Complete structural wiring
• Writing an exhaustive testbench

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Power Logic

• Registers used to shut down modules not in use
• Controls 3-input multiplier args
• Controls accumulator and output registers

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Next Steps

• Produce module schematics
• Continue optimizing logic
• Implement power logic control

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Work Distribution

• Tom Verilog implementation
• Dave Verilog implementation
• Greg Gate level multiplier, adder
• Kate Floor plan
• Bowei Destructive criticism

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Problems

• Looking into power gating
• Group members can only work for 10 hours straight
  before going insane or feral or both

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Questions
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References

• None for this week