Undetectable UWB Networks

1
Undetectable UWB Networks
Bob Brodersen Mike Chen Stanley Wang Ian
ODonnell Kathy Lu Dept. of EECS UC Berkeley

• http//bwrc.eecs.berkeley.edu

2
The problem of UWB interference

• Other users are upset (to say the least) about
  the potential of UWB transmissions in their band
• UWB transmission at Part 15 spectral mask levels
  would severely degrade narrowband systems
• How low should the requirement be?
• Make the transmission level so low that it is
  completely masked by kT thermal noise

3
Some numbers

• Received thermal noise level is -174dBm/Hz
• Over a 20 MHz band (lets take 802.11a as an
  example) the rms noise is 101dBm.
• The use of Part 15 EIRP levels would yield 91
  dBm at 8 meters (6dB of antenna gain)
• This gives a sensitivity loss of 10dB
• No wonder they are unhappy!
• (Bill McFarlin, Atheros Comm.)

4
One answer

• Transmit at power levels that do not degrade
  sensitivity (i.e. at levels so that the received
  signals at some distance are below the thermal
  noise level)
• Then the question is what data rate can we
  support?
• More numbers

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More numbers

• Capacity(AWGN) BW ln(1SNR)
• If SNR ltlt 1 then Capacity BW SNR
• For BW 3 GHz
• SNR .1
• Capacity 300 Mbits/sec
• (Not bad.)
• OK is this achievable???

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Realizing 300MBits/second

• Two issues
• Are we in the overspread regime where too much
  bandwidth causes a loss in capacity
• Is it implementable at low cost in a reasonable
  time frame?

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The Overspreading Story (Tse)

• As the bandwidth increases the number of resolved
  multipath rays, L, increases proportionally
  L (BW)T delay spread
• The coherence time, Tcoh, tells us how long the
  multipath remains stationary
• The energy available for estimation of the
  multipath components is PowerTcoh
• (These channel estimates are necessary to
  recover the energy using a rake receiver)

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The overspreading problem

• Therefore the energy to noise ratio of each ray
  decreases with increasing bandwidth and thus
  becomes increasingly difficult to estimate
• Multipath ray ENR PTcoh / (L No)
  PTcoh / (NoBWTd.s.)
• 1/BW

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When is it a problem?

• When happens when we get into an overspreading
  situation? (from Telatar and Tse)
• Critical parameter a PTcoh/(NoL)
• P Total power No Additive noise
• Tcoh Coherence time L of resolvable
  paths (gtgt1)
• If a ltlt 1 then Capacity a CAWGN
• What regime are we in???

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Implementation Issues

• To achieve the 300 Mbit/sec limit we need to A/D
  at twice the total bandwidth or 6
  Gsamples/second.
• We then need to perform 100, 100 point
  correlations at a rate of 300 Msamples/sec or 3
  1012 operations/second
• (100 rays in the rake, length 100 codes)
• Is that really possible?

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What are alternative architectures?
.1-1
1-10 MIPS/mW
Should be 10-100 MOPS/mW ??
Flexibility
Embedded Processor
DSP (e.g. TI 320CXX )
100-1000 MOPS/mW
Reconfigurable Processors (Maia)
Embedded
Factor of 100-1000
FPGA
Direct Mapped
Area or Power
Hardware
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Direct mapping architectures
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Energy and Area Efficiency Metrics

• Definition MOPs
• Millions of algorithmically defined arithmetic
  operations (e.g. multiply, add, shift, delay)
  in a GP processor several instructions per
  useful operation
• Figures of merit
• MOPs/mW - Energy efficiency
• MOPs/mm2 - Area(cost) efficiency
• What are these efficiencies for advanced CMOS
  using the most highly optimized architecture?

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What can a fully parallel CMOS solution
potentially do?

• In .13 micron a multiplier requires .02 mm2 and
  3pJ per operation at 1 V. Adders and registers
  are about 10 times smaller and 10 times lower
  energy
• Lets implement a 50mm2 chip using adders,
  registers and multipliers
• We can have 10,000 adders/registers and 500
  multipliers in about 1/2 of the chip, also assume
  1/3 of power goes into clocks
• 100 MHz clock (1 volt) gives 1000 Bops at
  150mW
• 3000 Mops/mW and 20,000 Mops/mm2

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Chip power and size

• What does it take to provide 3000 Bops?
• Power 3 x 1012 / 3000 Mops/mW 1 Watt
• Area 3 x 1012 / 20,000 Mops/mm2 150
  mm2
• Reasonable .

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Our Approach

• Transmission at below thermal noise levels
• use matched filter with processing gain to
  improve SNR
• Highly optimized analog and digital architectures
• Design and implement radio at frequencies up to
  60 GHz

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System Modeling

• Develop models for antenna, packaging and CMOS
  circuitry appropriate for UWB (wideband vs.
  narrowband approximations)
• Simulink model of complete baseline system to
  drive SShaft and Bee design flows

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Transmitter Modeling

• UWB antenna is not likely to be a purely
  resistive load and may strongly influence the
  transmitter circuits
• Antenna/circuit co-design is necessary
• Efficient pulse-shape design
• Taking pulse-shape design into account adds one
  more dimension to improve the performance of the
  antenna

Pulse Generator
Transmission Line
Bonding Wire
Antenna
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Receiver Modeling

• Design Front-end as one block
• Convert propagating EM wave into best possible
  signal at output of LNA

• Anti-alias filtering to A/D
• Gain for A/D
• 50 ohm model for antenna need UWB model

A/D
Lbondwire
Lg
Ls
Vb
Lbondwire
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Simulink System Simulation

• Transmit ideal Gaussian doublets modulated with a
  length 2200 code, whose chip time is 10ns at a
  2MHz rate
• Reception simple correlator

3-bit A/D fs3.3 GHz
fc1GHz
G57dB
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Undetectable UWB

• Real time waveforms in multipath with and w/o
  noise

Noisy
Noiseless
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Undetectable UWB

• Correlation profiles in multipath with and w/o
  noise
• First arrival signal arrives at 103 ns

Noisy
Noiseless
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Undetectable UWB

• Correlation profiles in analog and digital domain
  after 3 bit A/D

Digital Correlator
Analog Correlator
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Analog Circuits - Pulse Reception
Energy of Pulse is Contained in Small Time Window
Time
Only Need Limited Amount of Fast Sampling
Use Parallel Sampling Blocks
Have Rest of Time in Cycle to Process Samples
Do Digital Correlation
Minimum of Analog Blocks Run at Speed
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Proposed System Architecture
Based on Digital Sampling/Acquisition
Oscilloscopes
MAC
Data Recovery Synch Detect
S/H
A/D
CLK GEN
CONTROL
PULSE
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Power Budget for a Low Power version
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How do we do the digital design?

• New Software
• Generation of netlists from Simulink
• Merging of floorplan from last iteration
• Automatic routing and performance analysis
• Automation of flow as a dependency graph (like
  the UNIX MAKE program)

Simulink
elaborate
netlist
floorplan
macrolibrary
merge
autoLayout
route
layout
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Simulink for Design Entry
Time-Multiplexed FIR Filter

• Simulink is an easy sell to algorithm developers
• Closely integrated with popular system design
  tool Matlab
• Successfully models digital and analog circuits

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Example 1 Test Chip

• 300k transistors
• 0.25 mm
• 1.0 V
• 25 MHz
• 6.8 mm2
• 14 mW
• 2 phase clock
• 3 layers of PR hierarchy

Parallel Pipelined FIR Filter(8X decimation
filter for 12-bit 200 MHz SD)
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Example 2 CDMA Baseband Receiver

• 500k transistors
• 0.18 mm
• 1.0 V
• 25 MHz
• 1.1 mm2
• 21 mW
• single phase clock
• 5 clock domains
• 2 layers of PR hierarchy

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Test Bed for System Verification

• Goal Evaluation of algorithms
• Approaches
• Simulation inexpensive, but slow and inaccurate
  (Simulink)
• HW Prototyping accurate, but slow and expensive
  (Sshaft)
• HW Emulation fast, accurate, inexpensive
  (Bee)
• Our HW Emulator is called BEE

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Whats BEE?

• A real time hardware emulator built with multiple
  high density Field Programmable Gate Arrays
  (FPGAs) 5,000 Bops
• Designed to directly emulate the digital portion
  of the chip and interface with analog front-ends.
• Fully automated design flow from Simulink to FPGA
  configuration bit stream.

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BEE Architecture

• Processing Board
• Total 20 Xilinx VirtexE 2000 chips, 16 for
  processing, 4 for interchip routing 16 ZBT SRAM
  chips, 1MB each.
• Control module
• Intel StrongARM 1110, on board 10 Base-T
  Ethernet, Linux OS
• Radio Rx/Tx Boards
• UWB transceiver 1 GHz 4 bit A/D, ECL edge
  generator, discrete amplifiers
• Design Flow
• From Simulink MDL to FPGA bit stream

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BEE Processing Board
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BEE UWB Front-End

• 1 1.5 GHz A/D (4-8 bits)
• 1 ns pulse generation
• Modular front-end for evaluation to evolve over
  time

BPU
Radio RX
LVDS Transmitter
ADC
Radio TX
LVDS Receiver
DAC
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Conclusions

• Test circuits analog and digital to test out
  undetectable UWB operation
• Bee test bed fast evaluation of algorithms for
  base band processing
• Evaluation of UWB and frequency bands ranging up
  to 60 GHz
• Most importantly need to support a UWB approach
  which no one can logically object to because they
  cant detect it!
• http//bwrc.eecs.berkeley.edu