Package with 4valued logic

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• Package with 4-valued logic
• Signal Attributes
• Assertion
• Data Flow description

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Few more Examples of Simulation

• Build a library of logic gates
• AND, OR, NAND, NOR, INV, etc.
• Include sequential elements
• DFF, Register, etc.
• Include tri-state devices
• Use 4-valued logic
• X, 0, 1, Z
• Encapsulate global declarations in a package

Our goal is to Explain 4-valued logic
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Global Package

• Build a library of logic gates
• AND, OR, NAND, NOR, INV, etc.
• Include sequential elements
• DFF, Register, etc.
• Include tri-state devices
• Use 4-valued logic
• X, 0, 1, Z
• Encapsulate global declarations in a package

• PACKAGE resources IS
• TYPE level IS ('X', '0', '1', 'Z') --
  enumerated type
• TYPE level_vector IS ARRAY (NATURAL RANGE ltgt)
  OF level
• -- type for vectors (buses)
• SUBTYPE delay IS TIME -- subtype for gate
  delays
• -- Function and procedure declarations go here
• END resources

Next we build gates
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Two Input AND Gate Example

• USE work.resources.all
• ENTITY and2 IS
• GENERIC(trise delay 10 ns
• tfall delay 8 ns)
• PORT(a, b IN level
• c OUT level)
• END and2

ARCHITECTURE behav OF and2 IS BEGIN one
PROCESS (a,b) BEGIN IF (a '1'
AND b '1') THEN c lt '1' AFTER
trise ELSIF (a '0' OR b '0') THEN
c lt '0' AFTER tfall ELSE
clt 'X' AFTER (trisetfall)/2 END
IF END PROCESS one END behav
a
b
1 and X X
c
Observe that we use here three-valued algebra
0,1,X
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And Gate Simulation Results
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Tri-State Buffer Example

• USE work.resources.all
• ENTITY tri_state IS
• GENERIC(trise delay 6 ns
• tfall delay 5 ns
• thiz delay 8 ns)
• PORT(a IN level
• e IN level
• b OUT level)
• END tri_state

ARCHITECTURE behav OF tri_state IS BEGIN
one PROCESS (a,e) BEGIN IF (e
'1' AND a '1') THEN -- enabled
and valid data b lt '1' AFTER trise
ELSIF (e '1' AND a '0') THEN b
lt '0' AFTER tfall ELSIF (e '0') THEN
-- disabled b lt 'Z' AFTER thiz
ELSE -- invalid data or enable b lt
'X' AFTER (trisetfall)/2 END IF
END PROCESS one END behav
b
e
Observe that we use here four-valued algebra
0,1,X,Z
a
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Tri-State Buffer Simulation Results
ARCHITECTURE behav OF tri_state IS BEGIN
one PROCESS (a,e) BEGIN IF (e
'1' AND a '1') THEN -- enabled
and valid data b lt '1' AFTER trise
ELSIF (e '1' AND a '0') THEN b
lt '0' AFTER tfall ELSIF (e '0') THEN
-- disabled b lt 'Z' AFTER thiz
ELSE -- invalid data or enable b lt
'X' AFTER (trisetfall)/2 END IF
END PROCESS one END behav

• USE work.resources.all
• ENTITY tri_state IS
• GENERIC(trise delay 6 ns
• tfall delay 5 ns
• thiz delay 8 ns)
• PORT(a IN level
• e IN level
• b OUT level)
• END tri_state

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D Flip Flop Example

• USE work.resources.all
• ENTITY dff IS
• GENERIC(tprop delay 8 ns
• tsu delay 2 ns)
• PORT(d IN level
• clk IN level
• enable IN level
• q OUT level
• qn OUT level)
• END dff

ARCHITECTURE behav OF dff IS BEGIN one
PROCESS (clk) BEGIN -- check for
rising clock edge IF ((clk '1' AND
clk'LAST_VALUE '0') AND enable
'1') THEN -- ff enabled -- first, check
setup time requirement IF
(d'STABLE(tsu)) THEN -- check valid
input data IF (d '0') THEN
q lt '0' AFTER tprop qn lt '1'
AFTER tprop ELSIF (d '1') THEN
q lt '1' AFTER tprop qn lt
'0' AFTER tprop ELSE -- else invalid
data q lt 'X' qn lt
'X' END IF ELSE -- else
violated setup time requirement q lt
'X' qn lt 'X' END IF
END IF END PROCESS one END behav
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D Flip Flop Simulation Results

• USE work.resources.all
• ENTITY dff IS
• GENERIC(tprop delay 8 ns
• tsu delay 2 ns)
• PORT(d IN level
• clk IN level
• enable IN level
• q OUT level
• qn OUT level)
• END dff

ARCHITECTURE behav OF dff IS BEGIN one
PROCESS (clk) BEGIN -- check for
rising clock edge IF ((clk '1' AND
clk'LAST_VALUE '0') AND enable
'1') THEN -- ff enabled -- first, check
setup time requirement IF
(d'STABLE(tsu)) THEN -- check valid
input data IF (d '0') THEN
q lt '0' AFTER tprop qn lt '1'
AFTER tprop ELSIF (d '1') THEN
q lt '1' AFTER tprop qn lt
'0' AFTER tprop ELSE -- else invalid
data q lt 'X' qn lt
'X' END IF ELSE -- else
violated setup time requirement q lt
'X' qn lt 'X' END IF
END IF END PROCESS one END behav
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Assertion Statements

• assert condition
• report message
• severity level
• Ex.
• assert not (S '1' and R '1')
• report S and R are equal to
  '1'
• severity Error
• An assertion statement specifies a boolean
  condition to check, an error message and a
  severity indication.

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Assertion Statements

• When the condition is false, the error message is
  sent to the system output with an indication of
  the severity and the name of the design unit in
  which the assertion occurred.
• (Default message Assertion violation).
• The severity is of the type Severity_Level which
  has the values of
• Note,
• Warning,
• Error,
• and Failure. (Default se-verity level Error)
• In some VHDL system, unsatisfied conditions of
  severity Error or Failure cause the simulation to
  terminate.

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Using Assertions to Specify Timing Requirements

• Assertion statements can be used to specify
  timing requirements, such as set-up time and hold
  time.
• Example

If this condition is false report is printed
If data is NOT stable and clock1 then check if
clock is stable in hold time
When data changes during clock1 it cannot change
during hold time from clock change, this is OK
because it changed after hold_time
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• Signal related attributes

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Pre-defined Signal Attributes
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Signal Attributes event and last_value
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Short definitions of these and others Signal
Attributes

• SIGNALevent - returns True if an event occurred
  on this signal during this delta
• SIGNALactive - returns True if a transaction
  occurred this delta
• SIGNALlast_event - returns the elapsed time
  since previous event
• SIGNALlast_value - returns previous value of
  signal before last event
• SIGNALlast_active - returns time elapsed since
  previous transaction

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Signal Attributes that return Signals

• Delayed(t), Stable, Quiet and transaction

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Stable Attribute
Signalstable(time) creates a signal that is True
when the reference signal has no events for time
value
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Derived signal attribute
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Signal -Related Attributes

• VHDL contains a number of predefined attributes
  which are related to signals.
• They can be divided into two classes
• attributes which define signals themselves
• attributes which are functions to provide
  information about signals.

These attributes are signals themselves
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Examples of Using Attributes Detecting Edges
We use attribute event
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Measuring Pulse Width
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Measuring Pulse Width (cont)
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Measuring Setup Time
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Delay Parameterization
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Delay Parameterization

• Entities can be made parameterized by the use of
• GENERIC CONSTANTS
• They are passed to an instantiated component by
  its environment
• A generic constant can be used in computation,
  but remains fixed during simulation.

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Delay Parameterization- Structured Example
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Data Flow Descriptions in VHDL

• A data flow description consists of a set of
  concurrent signal assignment statements.
• A signal assignment statement executes in
  response to change on its input signals.

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Data Flow Descriptions in VHDL

• Each value in the waveform will be scheduled to
  appear
• on the target after the specified delay.
• If the assignment statement executes again,
  previously
• scheduled values may be overridden.
• A delay of zero represents an infinitesimally
  small delay
• signal assignment never takes effect immediately.
• Data flow descriptions are similar to
  register-transfer
• level expressions.
• They may imply hardware implementation
  structure.

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Simple data-flow example
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More examples of Concurrent Signal Assignment
Guarded will be discussed in a separate lecture
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More examples Concurrent Signal Assignment

• This describes a decoder, or translator from
  binary to one-hot code

We discussed it but now we add timing
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Conditional Signal Assignment
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Selected Signal Assignment

• concatenation

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For students to use and think about

• What is the basic timing model for simulation in
  VHDL.
• Types of delay in VHDL
• transport,
• inertial
• delay.
• Detailed explanation of delta model. Why previous
  models were inconvenient? The student should be
  able to assume delta delay draw the timing
  diagram and next go with delta to zero and
  illustrate graphically the results of simulation.

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For students to use and think about

• General assignment statements with bit
  selections, concatenations, timing delays and
  expressions.
• Variables versus signals in assignment
  statements.
• Some selected signal-related attributes.
• Conditional signal assignment with when.
• Concurrent signal assignment with when
• Explain simulation with four-valued simulator.
• Assertion statements.
• Detailed D FF with timing.
• Tri-state buffer and its simulation.

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Questions for students

• Example MUX
• This example highlights the difference between
  signals and variables

ARCHITECTURE test1 OF mux IS SIGNAL x BIT
'1' SIGNAL y BIT '0' BEGIN PROCESS
(in_sig, x, y) BEGIN x lt in_sig XOR y y
lt in_sig XOR x END PROCESS END test1
ARCHITECTURE test2 OF mux IS SIGNAL y BIT
'0' BEGIN PROCESS (in_sig, y) VARIABLE x
BIT '1' BEGIN x in_sig XOR y y lt
in_sig XOR x END PROCESS END test2

• Assuming a 1 to 0 transition on in_sig, what are
  the resulting values for y in the both cases?

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Sources

• VLSI. Ohio University, Starzyk

• Krzysztof Kuchcinski
• Yingtao Jiang
• Hai Zhou
• Prof. K. J. Hintz