A Delay Fault Model for AtSpeed Fault Simulation and Test Generation

1
A Delay Fault Model for At-Speed Fault Simulation
and Test Generation

• Irith Pomeranz
• Purdue University
• Sudhakar M. Reddy
• University of Iowa

2
Overview

• The Need for a New Delay Fault Model
• The Unspecified Transition Fault Model
• Fault Simulation
• Test Generation
• Experimental Results
• Conclusion

3
Application of Delay Fault Tests

• Scan based test application of two-pattern tests
  that start and end with scan operations.
• Single fast clock cycle SavirPatil, IEEE TCAD,
  Aug. 93, Aug. 94.
• Test sequences applied using only the functional
  mode of operation.
• Single fast clock cycle Devadas, ITC-89.
• All fast clock cycles (at-speed) PomeranzReddy,
  DAC-02.

4
At-Speed Test Application

• Advantage The circuit is tested under its
  functional operation conditions.
• Certain defects will only be detected when tests
  are applied at-speed.
• Overtesting due to detection of faults under
  non-functional operation conditions is avoided.

5
Transition Faults

• A simple model for spot defects affecting delays
  on gate inputs and outputs.
• For scan-based tests a transition fault is
  associated with a large extra delay that causes
  the delay of any path through the fault site to
  exceed the clock period.
• For at-speed tests it is necessary to consider
  the size of the extra delay (in numbers of clock
  cycles).

6
0?1 Fault on Line g
7
Transition Faults and At-Speed Tests

• Each transition fault must be associated with
  multiple sizes of 1,2, clock cycles Cheng, IEEE
  TCAD, Dec. 93.
• Fault simulation and test generation complexity
  increase accordingly.

8
Goal

• Develop a transition fault model where each
  transition fault is considered only once (no
  increase in the number of faults).
• A transition fault of the new model will
  encompass the behavior of transition faults of
  sizes 1,2,.
• N-detection fault simulation and test generation
  will increase the confidence that transition
  faults are detected.

9
Unspecified Transition Faults

• Similar to standard transition faults
• A fault is associated with every line g and
  signal-transition v?v.
• The fault gv?v is activated at time unit u1 if
  gv at time unit u and gv at time unit u1.

10
Unspecified Transition Faults

• Unlike standard transition faults
• When the fault is actived, gx.
• For every time unit where an x value reaches a
  primary output, the fault is potentially detected
  once.
• The higher the number of potential detections,
  the more likely it is that the corresponding
  standard faults are detected.

11
X-Value Injection / Propagation

• X-values accommodate the unknown duration of the
  fault.
• Injecting a new x value cannot mask an x value
  injected earlier.

12
Example u1 u2
a1
g1

y1

z,Y0
b0
a0
g0/x

y0

z,Y1/x
b0
n.det1
13
Example u2 u3
a0
g0/x

y0

z,Y1/x
b0
n.det1
a1
g1/x

y1/x

z,Y0/x
b0
n.det2
14
Example u3 u4
a1
g1/x

y1/x

z,Y0/x
b0
n.det2
a1
g0/x

y0/x

z,Y1/x
b0
n.det3
15
Example u5 u6
a1
g1/x

y1/x

z,Y0/x
b0
n.det4
a0
g0

y0/x

z,Y1
b0
16
Fault Simulation Results

• Compacted deterministic test sequences for
  stuck-at faults.
• All-zero initial state.
• Simulated faults
• Unspecified transition faults (up to n5
  detections).
• Stuck-at faults (up to n5 detections).
• Standard transition faults with an extra delay of
  a single clock cycle.

17
s526
18
b04
19
Additional Information

• A transition fault gv?v has a corresponding
  stuck-at fault g/v.
• In a combinational circuit, g/v is detected by
  the second pattern of a test for gv?v.
• The relationship between the numbers of
  detections of corresponding faults will provide
  guidelines for test generation.

20
Numbers of Detections (s298)
21
Test Generation

• Given a test sequence T. For d0,1,
• For every unspecified transition fault gv?v
  detected d times such that g/v is detected
• Extract a new test subsequence for g/v.
• Add it to T.

22
Test Generation Results
23
Test Generation Results
24
Conclusion

• A new transition fault model for fault simulation
  and test generation of at-speed test sequences.
• Associates a single fault with every standard
  transition fault.
• Fault activation is modeled by injecting
  unspecified values.
• Accuracy is increased by performing n-detection
  fault simulation and test generation.