Hardware Architecture Design and Implementation of RayTriangle Intersection with Bounding Volume Hie

1
Hardware Architecture Design and Implementation
of Ray-Triangle Intersection with Bounding Volume
Hierarchies

• Chuan Yiu Lee
• Advisor Prof. Shao-Yi Chien
• Media IC System Lab
• Graduate Institute of Electronics Engineering
• National Taiwan University

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The Focus

• Fully ray tracing pipeline is quiet large
• The most computation complex stage should be
  focused first
• Traversal
• Intersection

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Ray Casting Unit

• Controller
• Control input by traversal result
• FIFO
• buffer data to balance the different throughput
• Cache
• save the inter packet bandwidth
• Arbiter
• arbitrate different memory request by priority

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CHIP