A Survey on Architecture Description Languages

1
A Survey on Architecture Description Languages

• Basant K. Dwivedi

2
Outline

• Motivation
• Maril
• MIMOLA
• HMDES
• nML
• ISDL
• EXPRESSION
• LISA

3
Motivation

• Rapid design space exploration
• Automatic toolkit generation
• Compiler
• Simulator
• Assembler
• Disassembler
• Linker
• ASIP Synthesis
• HDL generation

4
Maril

• Maril was part of Marion retargetable code
  generator system.
• It was to study different instruction scheduling
  and register allocation strategies for RISC
  processors.
• Supported architectural features
• Storage units registers, memory
• Pipelines
• Functional units
• Instruction set
• Runtime model register usage
• The Marion system comprises of the code
  generator generator, the compiler front end and
  back end.

Maril 91
5
Maril (Cont.)
cwvm general (int) r general (double)
d allocable r15 calleesave r47 sp
r7 down arg (int) r2 1 arg (int) r3
2 arg (double) d1 1 result r2
(int) result d1 (double) CWVM
declare reg r07 (int) reg d03
(double) equiv r0 d0 resource
IFIDIEIAIW resource F1F2F3F4 def
const16 -3276832767 memory
m02147483647 Declerations
instr add r, r, r (int)
1 2 3 IF ID IE
IA IW (1, 1, 0) instr fadd.d d, d, d
1 2 3 IFID F1,ID
F1F2F3F4F5 IW,F5 IW (1, 6,
0) Instructions
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Maril (Cont.)

• Additional features
• Auxiliary latency directives
• Escape functions to write a C function to produce
  a sequence of individually schedulable
  instructions
• Glue transformations for tree-tree
  transformations prior to code selection
• Allows instruction scheduler to generate resource
  vector to avoid structural hazards
• What is lacking ?
• Only for RISC processors
• No structural information
• Memory specification is weak

7
MIMOLA

• Target CAD activities synthesis, microcode
  generation, test generation and simulation.
• MIMOLA 4.1 can be used as HLL, RTL, HDL or
  microprogamming language.
• Supports both structural and behavioral
  description
• HW structures as netlists
• Behavior as PASCAL like program
• One can provide initial simulation stimuli.
• The only built in data type is the bit vector.

MIMOLA 94
8
MIMOLA (Cont.)
MODULE simple_alu (IN a, b (30) IN ctr
(10) OUT result (30) OUT condition
(00)) BEHAVIOUR alu_behave IS CONBEGIN
result lt- CASE ctr OF 0 a 1 b 2 a
b 3 a - b END AFTER 1
condition lt- CASE ctr OF 0 a 0 1 b
0 2 a b 0 3 a - b 0
END AFTER 0 COEND MIMOLA description of a
simple 4 bit ALU
MODULE regfile (OUT outdata (30) IN
address (30) IN indata
(30) IN wr_enable (0) IN c
(30) ) BEHAVIOUR readregfile
IS VAR regs array0 .. 15 of (30) CONBEGIN
outdata lt- regsaddress CASE wr_enable
OF 0 NOLOAD regs 1 AT c UP DO
regsaddress indata END COEND MIMOLA
descritption of a simple regfile
9
MIMOLA (Cont.)

• Other features
• Hierarchical design specification
• Availability of timing models
• HW synthesizer and simulator is available
• Allows retargetable code generation
• Drawbacks
• The description is very low level.
• Extraction of instruction sets from the
  structure.
• It doesnt allow to specify constraints.

10
HMDES

• HMDES was designed to write machine descriptions
  for retargetable compilation and simulation.
• It uses a preprocessor based on C preprocessor
  and unix C shell language.
• Architectural components are described using
  SECTION.
• Back end tools support description of
• Traditional storage units registers, register
  files, cache
• Resource units and their usage
• Operation scheduling information using
  reservation tables
• One can also specify compiler-specific
  information such as register allocation
  information

HMDES 96
11
HMDES (Cont.)
SECTION Reg_file GPR( static(
for(N in 0 .. (gpr_static_size-1)) GPRN
) static( for(N in 0 ..
(gpr_static_size-1)) GPRN )
width(word_size)
speculative(speculation)
virtual(I) ) --
-- Register file specification
SECTION Resource_Unit RUNIT_ialu (use(ialu)
time(0)) Resource unit specification
SECTION Operation OP_FMULT1 alt(
(format(OF_Std1) reserv(RT_FPMUL1)
latency(OL_LAT1)) ) Operation specification
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HMDES (Cont.)

• Limited retargetability only for HPL-PD family.
• Explicit reservation table specification which is
  error prone.
• More general memory organization such as stream
  buffers, on chip DRAM, scratch pad memory etc.
  cannot be explored.
• Because of hierarchical specification local
  changes can propagate deep into the description.

13
nML

• The nML formalism describes instruction set as
  attributed grammer using AND and OR rules.
• Attributes
• with opn rules
• action
• image
• syntax
• with addressing mode rules
• effective address attribute apart from attributes
  with opn rules
• Supports pipelines using transitory storages
• Retagetable code generator and instruction set
  simulator can be derived.

nML 95
14
nML (Cont.)
OR-rule opn instruction computemove moveabs
ctrl AND-rule opn computemove(ccompute,
mmove)
opn shift(olopd, shint(3)) action
AS o AR AS ltlt sh opn
computemove(ccompute, mmove) image
0c.imagem.image syntax format( s
s, c.syntax, m.syntax) Operation attributes
specification
mem m1024, int(16) reg r4, fix(1,
31) Storage units
trn as1, int(16) delay 1 trn ms1,
int(32) delay 1 sync as Transitory storage
(pipelines)
15
nML (Cont.)

• No formal way to specify memory hierarchy.
• It doesnt support explicit pipelines.
• Structural information cannot be provided.
• Scheduling information such as reservation tables
  cannot be specified.

16
ISDL

• Target tools retargetable code generator,
  instruction set simulator and retargetable
  assembler.
• Description consists of following sections
• Intruction word format hardware instruction word
• Global definitions definitions used in later
  sections. It also allows to include some C code
  to emit some information.
• Storage resources declaration of registers and
  memories using depth and bitwidth information
• Assembly syntax definitions of operations using
  RTL descriptions, cost and timing
• Constraints illegal operation constraints
• Optimization information information like delay
  slot instructions, branch prediction hints etc.
• Drwabacks
• No structural information
• Pipeline and memory specification is weak

ISDL 96
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EXPRESSION

• It aims at generating software toolkit
  (retargetable compiler and simulator) for SOC
  design space exploration.
• Mixed structural-behavioral description.
• Explicit memory specification.
• Some amount for formal verification.
• Automatic reservation table generation.
• Supports variety of processor architectures.
• It doesnt support generation of the HDL for
  ASIP.
• There are no reports on simulation speed or
  quality of code.

EXPRESSION 98
18
EXPRESSION (Cont.)
(PIPELINE FETCH DECODE EX) (EX ALU Mult AGU1
AGU2) Pipeline Specification
(STORAGE_PARAMETERS (RFA (TYPE
REGFILE) (SIZE 2) (WIDTH 24) )
(L1_sram (TYPE SRAM) (SIZE 512) (WIDTH
12) (ADDRESS_RANGE 0 255) (ACCESS_TIME 2)
) -- -- ) Memory Specification
(OP_GROUP alu_ops (OPCODE add
(OP_TYPE DATA_OP) (OPERANDS (SRC1 g1)
(SRC2 g1) (DST g2)) (BEHAVIOR DST SRC1
SRC2) ) -- ) (VAR_GROUPS (g1
RFX) (g2 RFA RFB) (g3 RFY) (g4
X_mem Y_mem RFB) (g5 RFX
RFY) ) Operations Specifications
19
LISA

• The LISA system aims at generating HDL for the
  processor along with software toolkit including
  linker.
• It consists of following models to retarget the
  tools
• Memory model registers and memories
• Resource model resource usage of operations
• Instruction set model valid combinations of
  operations and admissible operands
• Behavioral model mainly for instruction
  selection and operation simulation
• Timing model pipeline specification and
  activation sequence of operations
• Microarchitecture model mainly for HDL
  generation of processor
• Supports compiled simulation.

LISA 01
20
LISA (Cont.)
OPERATION Neg_RM BEHAVIOR USES (IN
R OUT RAM)
RAMaddress (-1) Rindex
Resource Model
RESOURCE PROGRAM_COUNTER int PC REGISTER
signed int R0 .. 7
DATA_MEMORY signed int RAM0 ..
255 ---- Memory Model
OPERATION COMPARE_IMM DECLARE
LABEL index GROUP src1, dest register
CODING ob10011 indexobx5 src1
dest SYNTAX CMP src1 , index ,
dest SEMANTICS CMP(dest, src1, index)
Instruction Set Model
RESOURCE PIPE_LINE ppu_pipe FI ID EX
WB OPERATION WriteBack in ppu_pipe.WB
BEHAVIOR Rvalue PIPELINE_REGISTER(pp
u_pipe, EX/WB).ResultE Timing Model
21
LISA (Cont.)

• HDL for the processor is getting generated only
  for the control path and interfaces, datapath is
  still handwritten.
• There is no formal way to specify memory
  hierarchy.
• Improving quality of retargetable compiler and
  datapath synthesis has been projected as future
  works.
• There is no explicit backend support for
  consistency checking and formal verification.

22
References
Maril 91 David G. Bradlee et. a.l, The
Marion System for Retargetable Instruction
Scheduling, in Proc. ACM SIGPLAN91. MIMOLA
94 Steven Bashford et. al., The MIMOLA
Language Version 4.1, Technical Report,
University of Dortmund, September 1994. HMDES
96 John C. Gyllenhaal et. al., HMDES Version
2.0 Specification, Technical Report Impact-96-3,
1996. nML 95 A. Fauth et. al., Describing
Instruction Set Processors using nML, in Proc.
DATE95. ISDL 96 Srinivas Devadas et. al.,
ISDL An Instruction Set Description Language
for Retargetability, Technical Report, MIT,
1996. EXPRESSION 98 Peter Grun et. al.,
EXPRESSION An ADL for System Level Design
Explortion, Technical Report, UC Irvine,
September 1998. LISA 01 Andreas Hoffmann et.
al., A Novel Methodology for the Design of
Application Specific Instruction Set Processors
(ASIPs) Using a Machine Descritption Language,
in IEEE TCAD, November 2001.