A FaultIndependent Transitive Closure Algorithm for Redundancy Identification

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A Fault-Independent Transitive Closure Algorithm
for Redundancy Identification

• Vishal J. Mehta
• Kunal K. Dave
• Vishwani D. Agrawal
• Michael L. Bushnell
• ECE Dept., Rutgers University
• Piscataway, New Jersey, USA

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Talk Outline

• Problem statement
• Background
• Implication graph
• Partial implications
• Transitive closure
• Redundancy identification
• Node fixation
• Results
• Conclusion

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Problem Statement

• We make significant improvements in Redundancy
  identification of combinational circuits using
  partial implications and transitive closure.
• The new techniques have many other applications.

4
Background

• Implication graphs
• Chakradhar, et al., Book, 1990
• Larrabee, IEEE-TCAD, 1992
• Zhao, et al., IEEE-VTS, 1997
• Transitive closure
• ATPG Chakradhar, et al., IEEE-TCAD, 1993
• Redundancy, Agrawal, et al., ATS, 1996
• Partial implications
• Henftling, et al., ECAD, 1995
• Gaur, et al., DELTA, 2002

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Implication graph
An implication graph is a representation of
logical implications between pairs of signals of
a digital circuit.

• Nodes
• Two nodes per signal nodes a and a correspond to
  signal a.
• A node has two states (true,false) represents
  the signal state.
• Edges
• A directed edge from node a to b means a1
  implies b1.

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Building an Implication Graph
AB C 0
AC BC ABC 0

• If C is 1 then that implies that A and B must
  be 1, but the reverse is not true. Similarly,
  if either A or B is 0 then C will be 0. But
  if we want to represent the implications of A and
  B on C then partial implications are necessary.

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Partial Implications

? ANDing Node
Reference Henftling, et al., EDAC, 1995
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Observability Variables

• Observability variable of a signal represents
  whether or not that signal is observable at a PO.
  It can be true or false.

Reference Agrawal et al., ATS96
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Adding Observability Variables to Implication
Graph

OCOA BOA OCBOA 0
OB can be added similarly.
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Transitive Closure

• Transitive closure of a directed graph contains
  the same set of nodes as the original graph.
• If there is a directed path from node a to b,
  then the transitive closure contains an edge from
  a to b.

Transitive closure
A graph
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Stuck-at Faults

• This is a type of fault, which causes a line to
  hold a constant logic value, irrespective of
  change of state at previous stages.
• There are two types of stuck-at-faults
• Stuck-at-1
• Stuck-at-0
• Detection of a fault requires the fault to be
  activated and its effect observed at a PO.
• Fault a s-a-1 is detectable, if following
  conditions are simultaneously satisfied
• a 0
• Oa 1

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Redundant Faults

• A fault that has no test is called an untestable
  fault.
• Any untestable fault in a combinational circuit
  is a redundant fault because it does not cause
  any change in the input/output logic function of
  the circuit.
• Identification of redundant faults is useful
  because they can be removed
• from testing consideration, or
• from hardware

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Redundancy Identification

• ATPG based methods
• Use exhaustive test pattern generation to
  determine whether or not a target fault has a
  test.
• All redundant faults can be found, but the ATPG
  cost is high (exponential in circuit size).
• Fault independent methods
• Analyze circuit topology and function locally
  without targeting a specific fault.
• Less complex than ATPG, e.g., testability
  analysis.
• Many (not all) redundant faults can be found at a
  lower cost.

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Redundancy Identification by Transitive Closure
c
a
s-a-0
e
s-a-0
b
d
Circuit with two redundant faults
Implication graph (some nodes and edges not shown)
Implication Partial implication Transitive
closure edge
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Method Summarized

• Obtain an implication graph from the circuit
  topology and compute transitive closure.
• There are 8 different conditions on the basis of
  which a fault is said to be redundant.
• Examples
• If node c implies c then s-a-0 fault on line c is
  redundant.
• If node Oc implies Oc then c is unobservable and
  both s-a-0 and s-a-1 faults on line c are
  redundant.

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Graph Size and Complexity

• Direct Implications ?ki1 (2ni 2ni2) O(k)
• Partial Implications ?ki1 (ni 2ni2 ni3)
  O(k)
• Controllability nodes
• 2 PI k PO O(k)
• Observability nodes
• 2PI k PO ?ki1 fanout branches
  O(k)
• n number of inputs for the ith gate.
• k number of gates in the given circuit.
• Time complexity for computing transitive closure
  is O(k3), but Gaur et al. (2002) show that
  empirically it has linear complexity.

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Node Fixation

• Node fixation occurs when a signal implies its
  own complement, or vice-versa.
• Edges from all other nodes are added in the
  implication graph to model the unconditional
  fixation.

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Example - Node Fixation
s-a-1
s-a-1
s-a-0
s-a-1
e
g
s-a-1
f
s-a-0
s-a-1
Note Only some edges are shown

• Initially only 2 out of 7 redundant faults were
• identified.
• After the implementation of node fixation
• concept, g-(s-a-1) was identified.

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Contrapositive Rule

• If a signal p implies another signal q then q
  implies p (Zhao et al. VTS97).
• This rule gives more implications in the graph
  after the node fixation is implemented and we are
  yet to verify how many more redundant faults will
  be found.

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Benchmark Results
Identified redundant faults and computation time
Circuit C3540 S9234 s13207
Total Flts. 3428 6927 9815

• ATPG
• Flts. CPU s
• 24.6
• 803.7
• 151 806.5

• TC/par.imp.
• Flts. CPU s
• 2.7
• 13.5
• 74 39.0

• TC
• Flts. CPU s
• 5.9
• 9.8
• 9 11.2

• FIRE
• Flts. CPU s
• 93 11.9
• 20.6
• 55 23.2

ATPG TRAN, Chakradhar et al., IEEE-TCAD93,
Sparc 5 TC/par.imp. This paper, Sparc 5 TC
Agrawal et al., ATS96, Sparc 5 FIRE Iyer and
Abramovici, IEEE-TVLSI96, Sparc 2

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Limitation of Method

• Observability variable of a fanout stem is not
  analyzed.
• Only the redundant faults due to false
  controllability of fanout stem can be identified.

Three redundant s-a-0 faults identified
by transitive closure (uncontrollable signals)
Two redundant stem faults not identified by
transitive closure (unobservable stem)
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Conclusion

• Partial implications improve fault-independent
  redundancy identification present results are
  the best known.
• Transitive closure computation run times were
  linear in the number of nodes for benchmark
  circuits (Gaur et al., DELTA02) -- the known
  worst-case complexity is O(N3) for N nodes.
• Further work has shown that many unobservable
  fanout stems can be identified from transitive
  closure analysis.

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• THANK YOU