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Hardware Considerations

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9/23/09. 1. Hardware Considerations. Chapter 2. 9/23/09. 2. Topics. Last lecture leftovers. What is XINU? What is Embedded XINU? What is a Linksys router? ... – PowerPoint PPT presentation

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Title: Hardware Considerations


1
Hardware Considerations
  • Chapter 2

2
Topics
  • Last lecture leftovers
  • What is XINU? What is Embedded XINU? What is a
    Linksys router? What is an openWRT? What can we
    do with all these?
  • Installment 1
  • Hardware consideration Chapter 2

3
Sample real-time systems
  • Lets discuss the sample systems listed in the
    text books.
  • We will also go over the exercises at the end of
    chapter 1.

4
XINU and Router
  • Xinu is a small, elegant system that follows a
    hierarchical structure. http//en.wikipedia.org/wi
    ki/Xinu
  • Router lets look at relationship between network
    protocol layering and a router.
  • Wireless router Access points, wireless
    communication
  • WRT54GL Wireless broadband router
  • Link
  • Embedded Xinu
  • Its goal is to port the XINU Operating System to
    the MIPS platform by specifically targeting
    LinkSys WRT54GL routers.
  • http//xinu.mscs.mu.edu/
  • OpenWRT
  • OpenWRT is essentially a Linux distribution for
    embedded systems, specifically routers.
  • http//xinu.mscs.mu.edu/OpenWRT

5
Protocol Layering and function of a router (From
Cornell Univ.)
Browser process
Web server process
Physical Link 1
Physical Link 2
6
Protocol layering Router
Browser wants to request a page. Calls HTTP with
the web address (URL). HTTPs job is to convey
the URL to the web server. HTTP learns the IP
address of the web server, adds its header, and
calls TCP.
Browser process
Web server process
HTTP
HTTP
H
TCP
TCP
IP
IP
IP
Link1
Link1
Link2
Link1
Physical Link 1
Physical Link 2
7
Protocol layering and Router
TCPs job is to work with server to make sure
bytes arrive reliably and in order. TCP adds its
header and calls IP. (Before that, TCP
establishes a connection with its peer.)
Browser process
Web server process
HTTP
HTTP
TCP
TCP
H
T
IP
IP
IP
Link1
Link1
Link2
Link1
Physical Link 1
Physical Link 2
8
Protocol layering and router
IPs job is to get the packet routed to the peer
through zero or more routers. IP determines the
next hop from the destination IP address. IP adds
its header and calls the link layer (i.e.
Ethernet) with the next hop address.
Browser process
Web server process
HTTP
HTTP
TCP
TCP
IP
IP
IP
H
T
I
Link1
Link1
Link2
Link1
Physical Link 1
Physical Link 2
9
Protocol layering and router
The links job is to get the packet to the next
physical box (here a router). It adds its header
and sends the resulting packet over the wire.
Browser process
Web server process
HTTP
HTTP
TCP
TCP
IP
IP
IP
Link1
Link1
Link2
Link1
Physical Link 1
Physical Link 2
H
T
I
L1
10
Protocol layering router
The routers link layer receives the packet,
strips the link header, and hands the result to
the IP forwarding process.
Browser process
Web server process
HTTP
HTTP
TCP
TCP
IP
IP
IP
H
T
I
Link1
Link1
Link2
Link1
Physical Link 1
Physical Link 2
11
Protocol layering router
The routers IP forwarding process looks at the
destination IP address, determines what the next
hop is, and hands the packet to the appropriate
link layer with the appropriate next hop link
address.
Browser process
Web server process
HTTP
HTTP
TCP
TCP
IP
IP
IP
H
T
I
Link1
Link1
Link2
Link1
Physical Link 1
Physical Link 2
12
Protocol layering and router
The packet goes over the link to the web server,
after which each layer processes and strips its
corresponding header.
Browser process
Web server process
HTTP
HTTP
H
TCP
TCP
H
T
IP
IP
IP
H
T
I
Link1
Link1
Link2
Link1
Physical Link 1
Physical Link 2
H
T
I
L2
13
Wireless LAN configuration From Colouris
14
WRT54GL Wireless router from Linksys
  • Firmware running the operations
  • Need to communicate with the firmware
  • Update the firmware
  • Load OpenWRT/XINU or other home brewed code into
    the router
  • Need basic access through a serial port to the
    firmware
  • Need console access to the firmware
  • That is the purpose of the hardware update you
    will be doing.

15
Hardware Basics
  • Von Neumann Architecture
  • Hardware interfacing
  • Latching recording the appearance of a signal
    for later processing
  • Edge vs. level triggering
  • Tristate logic high, low, tristated
  • Wait state
  • System interfaces and buses address, data,
    control (2.2.5)
  • Universal asynchronous synchronous relay terminal
    (UART) is typically used for parallel to serial
    transfer
  • See Fig. 2.3

16
Standard Interfaces
  • MIL-STD-1553B
  • Small Computer system interface (SCSI)
  • IEEE 1394 firewire

17
MIL-STD-1533B
  • Widely used in military and commercial avionics
  • Specifies hardware configuration and transmission
    and receipt protocols
  • 1533-bus protocol is a master-slave protocol one
    module on the bus acts as a master and others as
    slaves and respond to masters commands.
  • Coupling of the devices is such that one device
    failure does not affect the others.
  • Master puts out device number followed by the
    packets to that device.
  • Also standard provides specification for handling
    of failure of the master.
  • See 2.3 and 2.4

18
SCSI (Scuzzy)
  • Parallel interface to many devices
  • SCSI 1, 2, 3, narrow, wide, fast , ultra,
    ultra-2, ultra-160
  • SCSI supports daisy chained devices
  • SCSI supports Fiber Channel and Firewire besides
    familiar ribbon cable
  • Daisy chained devices can communicate
    independently
  • Device 0 is the boot device and other devices get
    non-0 id.
  • Examples interfaces to hard drive, CDROMs,
    scanners and other peripherals

19
IEEE 1394 Firewire
  • Standard specifies very fast external bus that
    supports data transfer rates of up to 400
    megabits per sec. (1394a) and 800 Mbps in 1394b.
  • Apple developed the technology
  • Can connect up to 63 devices
  • Multiple speeds on single bus, thus avoiding
    daisy chaining and peer-peer
  • Hot pluggable devices can be added and removed
    when the bus is active
  • Two types of transfer asynchronous and
    isochronous
  • Isochronous data transfer at predetermined rate
    multimedia applications used in cameras, VCRs,
    televisions, audio devices

20
Memory Technologies
  • Ferrite core (dinosaur of memories)
  • Semiconductor memory (RAM)
  • Fusible link ROM and nonvolatile
  • UVROM ultra violet erasable ROM
  • EEPROM Electronically erasable PROM
  • Flash memory rewritable PROM that uses single
    transistor per bit commonly used in embedded
    real-time applications.
  • Ferroelectric RAM 40ns access times, 64 Mbyte
    arrays.

21
Memory organization and map
FFFFFFFF
FFFFFF00
FFFFFE00
FFC00000
E0000F00
E0000000
00000000
22
Input/output
  • Programmed input/output an IN instruction will
    transfer data from input device to a CPU
    register. An OUT instruction does the opposite.
  • Example to control the speed of a motor
    (controller) connected to system in the device
    space as programmed IO
  • LOAD R1, speed
  • LOAD R2, motoraddress
  • OUT

23
Direct memory access (DMA)
  • When using a DMA, access to the computers memory
    is given other devices in the system without CPU
    intervention.
  • Fig. 2.11 lets discuss its circuitry and
    operation.
  • DMA timing in Fig.2.12

24
Memory mapped IO
  • Does not require special IN and OUT operation.
  • Certain designated locations of memory appear as
    virtual IO ports.
  • For controlling the speed of a stepper motor
  • LOAD R1, speed
  • STORE R1, motor_address
  • Where speed is a bit mapped command as shown in
    fig. 2.14
  • Bit 0 light on
  • Bit 1..3 control other devices
  • Bit 4..7 stepper motor speed (4 bits for 16
    different speeds)

25
Interrupts
  • Interrupts are signals generated to indicate
    exceptional events.
  • Internal and external interrupts
  • Instruction support for interrupts enable and
    disable interrupts
  • Internal CPU handling of interrupts Current
    state including PC is saved and the control is
    transferred to ISR (interrupt service routine).
  • What to do when dealing with multiple external
    devices all working asynchronously with the CPU?
  • Use a programmed interrupt controller (PIC).
  • Fig.2.17
  • Also lets look at interfacing devices using PIC
    Fig. 2.20 and Fig.2.21

26
Enhancing Performance
  • Exploit locality of reference paging heavily
    used cell phones and networked handheld devices
  • Cache recent computations, current data set,
    current locality of instructions
  • Pipelining used in RISC processors
  • Coprocessors for special processing digital
    signal processing (DSP), fast Fourier transforms
    (FFT), etc.

27
Transducers
  • Transducers are devices that convert energy from
    one form to another.
  • Temperature sensors (or any sensor)
  • Accelerometer compression of piezoelectric
    device is exploited to convert the compression of
    an electrical signal.
  • Position resolvers
  • A/D converters

28
Summary
  • We studied hardware considerations for embedded
    and real time systems.
  • Hardware choices and design of the various
    controllers have significant effect on the
    performance of a RT embedded systems.
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