EE 551 Project

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EE 551 Project

• A Versatile Calculator

Anusha Atla Simi Mohanty
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Design Flow
REQUIREMENTS
ARCHITECTURAL SPECIFICATIONS
STRUCTURAL DESCRIPTION
BEHAVIORAL DESCRIPTION
TECHNOLOGY LIBRARIES
SYNTHESIS
PHYSICAL SPARTAN
PROTOTYPE SPARTAN
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I/O Description
Dip Switch
7 SEG
7 SEG
SPARTAN3
Push Button1
7 SEG
7 SEG
Push Button2
CLK
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System Requirements

• Power-up test
• 16 bit instruction set
• - 3 Bit Operation codes
• Add 000
• Sub 001
• AND 010
• OR 011
• XOR 100
• Mul 101
• Div 110
• - 6 bit Operand 1
• - 6 bit Operand 2
• Output on 7 Segment displays

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Built In Self Test

• Power-up default mode
• Lights up all the LEDs
• BIST mode accessible by pressing the Push
  Button 2.
• Pressing Push Button 2 again will return the
  main controller to RUN mode.

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System Modules

• Input Processing
• Mode Control
• Main Controller
• Memory Unit
• Computation Module
• Output Processing Unit

Instruction Splitter
data1
InstructionCode
data2
Opcode
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System Block Diagram
Memory
Computation Module
Dip Switches
Input Processing Module
Push Buttons
Main Controller
Built-in Self-Test Module
External Clock
Mode Control Module
7-Segment Displays Decoder / Controller Module
7-segment LED displays