CSCE 611: Interrupts and Exception Handling

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CSCE 611Interrupts and Exception Handling

• Instructor Jason D. Bakos

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Interrupts and Exceptions

• Events other than branches that change the normal
  flow of instruction execution
• Exceptions
• Unexpected event from inside the processor
• Arithmetic overflow, divide-by-zero
• Invalid instruction or fetch alignment error (bus
  error)
• L/S address error (misalignment, attempted access
  to protected memory)
• Reserved/privileged instruction
• Syscall (invoking the OS from user program)
• Breakpoint
• Interrupts
• Unexpected event from outside the processor
• I/O device request
• Timer

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Exceptions

• We will implement
• Arithmetic overflow
• add, addi, sub
• Use overflow output from ALU
• Write-back result?
• System call
• OS services
• I/O, process control, process synchonization
• Invalid instruction
• Invalid opcode/function code
• Lowest priority, unconditional transitions

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Interrupts

• Must implement way for external devices to get
  the processors attention
• Assume 1 external interrupt
• Signals processor through IRQ input
• Processor signals completion through IACK output
• Want to complete current instruction before
  servicing interrupt

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Interrupts and Exceptions

• What to do?
• Execute code in response to event (handler)
• Save PC (EPC reg,)
• Record cause (Cause reg.)
• Disable e/i (shift Status reg.)
• Set new PC (4)
• Return from handler
• Restore PC
• Enable e/i (shift Status reg.)
• Determining type of exception
• Use vectored exceptions
• Infer type from address
• Use polled exceptions
• Use Cause register
• This is what MIPS does

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Required Hardware

• Hardwired handler address
• EPC register
• Address of instruction that caused exception 4
  (PC)
• Cause register
• 32-bit register that holds cause of exception
• Status register (shiftable)
• Use for disabling interrupts and exceptions
• Additional control and datapaths

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Cause Register

• Use last 2 bits

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Status Register

• Use last 4 bits

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Control

• When an exception or interrupt occurs, must have
  a state where
• EPC lt PC
• Cause lt (cause)
• Status lt Status ltlt 4
• PC lt (handler address)
• Return
• PC lt EPC
• Status gtgt 4
• How to add states?

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Required Hardware
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Required Instructions

• EPC, Status, and Cause registers
• Instruction set treats these registers as being
  on coprocessor 0
• Status (12), Cause (13), and EPC (14)
• To use these registers, well implement two
  instructions
• mfc0 rt, rd
• mtc0 rd, rt
• Datapath analysis for these instructions?

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Required Instructions

• Also, we need a syscall instruction to implement
  system calls
• syscall
• Syscall call value in v0
• Return from exception
• rfe

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Notes

• Due date is Friday, April 27
• What to turn in
• Waves from testbench run