Computer Architecture: Development Tools for Multiprocessor FPGA Designs

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Computer ArchitectureDevelopment Tools for
Multiprocessor FPGA Designs
Daniel Raible David Avanesian Dragos
Dinca EEC-581 Final Project Presentation
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Field Programmable Gate Array (FPGA)

• Xilinx Spartan-3
• ISE development software
• 5 million gates
• 104 hardware multiplier modules
• 30 x 30 ball grid array (BGA)
• Up to 400MHz clock speeds

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Uniprocessor Limitations

• Growing embedded processing requirements are
  turning system architects toward multiprocessor
  designs, or Chip Multiprocessing (CMP) FPGA
  Solutions
• High logic density
• Parallel computing capacity
• Dedicated hardware accelerators
• Customizable

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Multiprocessor FPGA Benefits

• Multiple Independent Functions various process
  modules
• Control Plane Offload real-time tasks
• Data Plane Offload intense calculations
• Interface Processing bridging
• Stream Processing pipelining for throughput
• Symmetric Processing partitioning for
  scalability
• Reliability and Redundancy distribution

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Available FPGA Hard Soft Cores

• Xilinx
• MicroBlaze 32-bit Harvard RISC soft-core
• PicoBlaze 8-bit RISC soft-core
• PowerPC 405 32-bit Harvard RISC hard/soft-core
• Altera
• Nios 16-bit RISC soft-core
• Nios-2 32-bit RISC hard/soft-core
• OpenCores.org, etc.
• Plasma 32-bit RISC soft-core
• OpenRISC1000 64-bit RISC soft-core

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Overall Multiprocessing Topology
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Design Flow
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Communication and Synchronozation(Xilinx
proprietary)
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Development Problems

• VHDL requires levels of abstraction to accomplish
  complex tasks
• Implementing and debugging just a single-core
  processor can be a daunting task
• Synchronization and coherency between
  heterogeneous cores/chips is complicated
• Compatibility between different IP cores
• Complete optimization takes a long time, and
  reduces flexibility

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Development Tools

• Automatic microarchitecture customization
• Configuration using TDM-MPI
• Dynamic reconfiguration

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Automatic Microarchitecture Customization

• Treats the problem as a multi-objective
  constrained integer nonlinear optimization
  problem.
• Architecture is an array of cost functions
• Runtime
• Power consumption
• Energy dissipation
• Cache misses
• Branch mispredictions
• Correlates application runtime to MA features
• Provides a search space for the developer

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Automatic Microarchitecture Customization
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Configuration Using TDM-MPI

• Uses an application compiler to optimize the
  architecture in the FPGA
• Efficient programming model
• Flexible design flow
• Can homogenize a system for the developer
• Selects the best hardware engines
• Selects the communications between them
• Transparent to the programmer

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Configuration Using TDM-MPI
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Dynamic Reconfiguration

• Exploits the reconfigurable nature of the FPGA
• Partial reconfiguration during run-time (DPR)
• Reduces optimization time
• Adds generality / flexibility
• Supported by Xilinx Virtex4

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Dynamic Reconfiguration
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Future Tools

• Decreasing placement time / compilation
• Increase abstraction / usability
• Developing OTS multi-core modules
• Complete GUI development interface, drag drop
• Pre-determined application optimizations /
  compromises
• Implement architecture standards (IEEE?)
• Encourage 3rd party development
• Cores, multi-cores
• Compilers

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Thank-You Friends!

• Questions?