CPU Scheduling Examples

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CPU Scheduling Examples

• Question 5.4, Page 187 of Text

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Arrival Order P1, P2, P3, P4, P5 all at time 0
FCFS
P1
P2
P3
P4
P5
10
0
11
13
14
19
Turnaround times
10, 11, 13, 14, 19
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Arrival Order P1, P2, P3, P4, P5 all at time 0
FCFS
P1
P2
P3
P4
P5
10
0
11
13
14
19
Waiting Times
0, 10, 11, 13, 14
A.W.T
(010111314)/5 48/5 9.6
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Arrival Order P1, P2, P3, P4, P5 all at time 0
SJF
P1
P2
P3
P4
P5
1
0
2
4
9
19
Waiting Times
9, 0, 2, 1, 4
A.W.T
(90214)/5 16/5 3.2
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Arrival Order P1, P2, P3, P4, P5 all at time 0
Nonpreemptive Priority (1 is highest)
P1
P2
P3
P4
P5
1
0
6
16
18
19
Waiting Times
6, 0, 16, 18, 1
A.W.T
(6016181)/5 41/5 8.2
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Arrival Order P1, P2, P3, P4, P5 all at time 0
RR (quantum1)
P2
P3
P4
P5
P1
P1
P3
P5
P1
P5
P1
P5
P1
P5
P1
1
0
3
2
5
4
7
6
9
8
10
11
12
13
14
19
Waiting Times 421119, 1, 235, 3,
421119

A.W.T
(91539)/5 27/5 5.4
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Summary
If context switches are expensive, how does this
affect the ranking of the algorithms in the chart?
Only RR is preemptive, thus the average waiting
time of the RR algorithm may increase due to
many context switches.
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Memory Hierarchy
http//www2.cs.uregina.ca/hamilton/courses/330/no
tes/memory/MemoryHierarchy.html
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Cache Memory

• A cache is a very fast block of memory that
  speeds up the performance of another device.
• Frequently used data are stored in the cache. The
  computer looks in the cache first to see if what
  it needs is there.
• Level 1 Cache is located directly inside the CPU
  itself, and stores frequently used data or
  commands.
• Level 2 Cache is located on the motherboard. It
  stores frequently used data from the computer's
  main memory (RAM).

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Simple Paging
Logical Memory
Physical Memory
Page Table
Logical Address Space 24
Page size 22
gt Use first (4-2) 2 high-order bits from
logical address for p, the page table
index gt Use remaining 2 bits for d, the page
offset
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Simple Paging
Logical Memory
Physical Memory
Page Table
Ex. Logical address 11 1110 10112
p 102 210 d 112
gt page table 110 012
gt physical address 01112 710
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Segmentation Hardware
Segment Table
s
CPU
s
d
Physical Memory
yes
lt

no
Error