HY220

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HY220
System Design Flow
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Transistor ??µ??? µ???da ?????µat?? (chip)
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?a??de??µa Inverter
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Chip ???f?? transistors - ?e???????a
Intel processor 10 000 000 p??e?
41 mux 10 p??e?

• ? te???????a (process) p?? ???s?µ?p????µe ??a t??
  ?atas?e?? (fabrication) ?a?????e? t?? pa?aµ?t????
  t?? transistors ?a? t? µe?e??? t??. ?a???
  ße?t???eta? ? te???????a
• µ???a??e? t? µ??e??? t?? transistor (pe??ss?te?a
  transistors st?? ?d?? ????)
• a????eta? ? ta??t?ta t??
• e?att??eta? ? ?ata????s? e????e??? t??.

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System design flow
System specification (functionality, timing)
C description (Golden Model)
Block partitioning
HDL code (verilog)
Full Custom transistor level (Memories)
Synthesis (Standard Cells)
Hardware Implementation (next slides)
Floorplanning
Place and Route
System Testing (functionality, timing)
Chip Prototyping
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Hardware Design Methods
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1. Full-Custom

• The transistor-layout is fully handmade, using a
  VLSI editor. Only useful for small designs due to
  the large expenditure.
• Maximal freedom
• High performance blocks
• Slow

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2. Array-Based (Gate-Array)
Large arrays of transistors are provided by the
ASIC vendor. Connecting these transistors in a
specific way results in the desired logic.
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Programmable Logic Array (PLA)

• PLAs have configurable AND-plane OR-plane.
• Can implement any 2-level AND-OR circuit.
• Efficient physical implementation in CMOS.

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Programmable Logic LUT
A mux selects which element of memory to send to
output
Really just a 1-bit memory
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FPGA Field Programmable Gate Array

• CLBs can be connected to passing wires.
• Wire segments connected by switch matrix.
• Long wire segments used to connect distant CLBs.
• Configuration information stored in SRAM bits
  that are loaded when power turns on.

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FPGA - Routing
CLB
CLB
1
00
1
CLB
CLB
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Whats in a CLB (LE)?
Carry out

• Programmable Logic
• Fixed Logic

Out
MUX
Inputs
LUT
0
1
Clk
Enable
Carry in
LE example
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Programming FPGA

• Lookup table implements logic functions.

0123
1
0
1

• Multiplexors and pass transistors implement
  routing.

• Switch matrix contains configurable clusters of
  pass transistors.
• provides wide variety of routing options

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Example Xilinx FPGA - Wires
Types of Interconnect
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Example Xilinx Configurable Logic Block
Clock EdgeSelect
Set/ResetControl
Clock EnableControl
Flip Flop
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Example Xilinx FPGA
Note CAD tools do PR, not designers
Direct connections
Internal 3-state Bus
Long lines and Global lines
Buffered Hex lines (1/6 blocks)
Single-length lines
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Block RAM (Extra RAM not using LUTs)
Spartan-IIE Block RAM
Port A
Port B

• Most efficient memory implementation
• Dedicated blocks of memory
• Ideal for most memory requirements
• Use multiple blocks for larger memories
• Builds both single and true dual-port RAMs
• CAD tool provides custom-sized block RAMs
• Quickly generates optimized RAM implementation

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Example Virtex-II Pro (Xilinx)
BRAM
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FPGA Modern Design Methodology
always mumble mumble blah blah
gates, gates, gates,
Synthesis
Synthesizable Verilog
Place and Route
LE 1
LE 2
Logic Elements in FPGA Chip
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What Do We Mean by Synthesis?

• Logic synthesis
• A program that designs logic from abstract
  descriptions of the logic
• takes constraints (e.g. size, speed)
• uses a library (e.g. 3-input gates)
• How?
• You write an abstract Verilog description of
  the logic
• The synthesis tool provides alternative
  implementations

constraints
Verilog blah blah blah
synthesis
or
library
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An Example

• Whats cool?
• You type the left, synthesis gives you the gates
• It used a different library than you did.
  (2-input gates only)
• One description suffices for a variety of
  alternate implementations!
• ... but this assumes you know a gate level
  implementation thats not an abstract Verilog
  description.

module gate (f, a, b, c) output f input a, b,
c and A (a1, a, b, c), B (a2, a, b,
c), C (a3, a, o1) or D (o1, b, c), E (f,
a1, a2, a3) endmodule
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Automatic Logic Synthesis

• Verilog synthesis may frequently interpret code
  differently from Verilog simulation
• Unneeded Logic May Not Be Detected
• Both circuits are equivalent

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Synopsys (Synthesis and Libraries)

• Synopsys tool can synthesize hardware for the
  components in a wide variety of libraries, as
  well as for complex programmable logic devices
  (CPLDs) and field-programmable gate arrays
  (FPGAs)
• Synopsys uses a basic library with simple gates
  and blocks. The manufacturer adds components
  (standard cells) to the library.

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Mapping and Routing

• Mapping Map logic produced by synthesis to
  logic elements, transforming the logic as needed
• Place Route Place logic in a particular
  combinational Logic Block on an FPGA, such that
  the wiring delay between the block and others is
  acceptable
• Must place critical circuit portions together to
  minimize wiring delays
• Propagation delay of signals depends
  significantly on routing delay

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Partitioning-Floorplanning
Floorplanning
Chip (abstract level)
Partitioning into blocks
MC
PP
DB
I
Place them in floorplanned area
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3. Cell-based Implementation Flow
always mumble mumble blah blah
Synthesizable Verilog
Synthesis standard- cells
Place and Route layout of cells
gates, gates, gates,
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Cell-based Design (or standard cells)
Semi-custom tool-based approach, where all cells
corresponding to the same type use the same
layout.
The height of each standard cell is fixed.
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Layout of Standard Cell
The layout of a standard cell from a
standard-cell library.
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Application Specific Integrated Circuit
A chip specific for a single application. Can not
be reused (reprogrammed) for other purposes.
Fabricate
Provide the layout with custom or semi-custom
blocks to the manufacturer.
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NRE and unit cost metrics
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ASIC VS FPGA

• FPGA (gate-array)
• Low startup cost
• Low financial risk
• Quick Manufacturing turnaround (reprogram)
• Easy Design Changes
• Can be reprogrammed
• Slow Clock
• Small on chip capacitance
• ASIC (full-customsemi-custom)
• High cost
• Slow Manufacturing turnaround (1 month)
• Long manufacturing time
• Compact design
• Fast clock