CMOS Optical Links ORS

1
CMOS Optical LinksORS

• Samuel Palermo, Azita Emami-Neyestanak, Hae-Chang
  Lee, and Mark Horowitz
• Stanford University

2
Overview

• High Speed Links
• Introduction to electrical links
• Limitation of electrical links
• Benefits of optical links
• Optical link architecture
• Optical Transmitters
• VCSEL and Modulator drivers
• Trends in data rate, power, and supply voltage
• Optical Receivers
• Comparison of different front ends
• Projection of power and area of RX in the future
• New receiver for optical routers

3
High Speed Electrical Links

• Necessary to equalize the growing disparity
  between on-chip computation and chip-to-chip
  communication bandwidth
• Components
• High-bandwidth transceiver (TX, RX)
• Terminated channel
• Precise clock generation and recovery

4
Limitations of Electrical Links (1)

• Maximum on-chip clock frequency that can be
  propagated without swing attenuation
• Clock period limit ? 6 8 FO4 inverter delays
• 0.25? CMOS ? 750 1000ps ? 1 1.3GHz

5
Improving Data Rate

• Multilevel signaling
• Requires small proportional noise sources
  (reflections cross-talk) due to reduction in
  SNR
• Time-interleaved multiplexing
• Requires multi-phase clock generation with low
  static phase offset and jitter
• Improvement is still less than 10X

6
Limitations of Electrical Links (2)

• Limited bandwidthdistance product of wires
• Proportional noise sources
• Reflections
• Cross-talk
• Power Consumption 30mW/Gb/s

(D. Miller and H. Ozaktas, J. Parallel Distrib.
Comput., 1997)
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Benefits of Optical Links

• Better Channel
• Longer Distances (SMF)
• Less attenuation per distance (0.2dB/km)
• Almost zero frequency dependant loss
• Dispersion Limited
• Chromatic (5ps/nm/km)
• Lower Power
• Less attenuation
• Less Noise
• No crosstalk between fibers
• No reflections

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Multi-Gbps CMOS Optical Link Architecture
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VCSEL Optical Source

• Optical power a linear function of laser diode
  current once biased above threshold
• High contrast ratio can be achieved by biasing
  close to threshold
• High frequency operation requires biasing the
  VCSEL above threshold to avoid turn-on delay
• Optical frequency response proportional to

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VCSEL Electrical Model
Small Signal Model

• Device electrical bandwidth dominated by bias
  dependent RJCJ
• RJ 30 - 100?
• CJ 0.5 1pF
• ? 40 70ps
• Total series resistance between 50 - 100? means
  low voltage swing for power levels appropriate
  for short optical interconnects
• Parasitic inductance causes current ringing
  reduced voltage headroom
• Device requires current driver with adequate
  range to handle variations in threshold current
  and slope efficiency

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TX VCSEL Driver Output

• Differential current steering driver minimizes
  power supply noise
• 8 bit control for bias modulation currents
• Current range from 0 5mA with 20?A resolution
• 3.3V output stage to keep current sources
  saturated due to VCSEL VF

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TX - VCSEL Driver Simulation Results

• Simulations with IBIASIMOD1mA
• Adequate bandwidth for 5Gbps data
• Area 300? x 520?

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External Modulation with MQWM

• Intrinsic quantum well region in the p-i-n region
  is absorbing
• Static reverse bias gives a photodetector
• Changing bias shifts the absorption edge - due to
  thequantum-confined Stark effect - and
  modulation occurs

(figure and data courtesy of G. Keeler, EE,
Stanford)
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MQWM Electrical Model

• Model simplifies to only a lump capacitor
  composed of the diode capacitance and parasitic
  bonding capacitance
• Assuming between 50 200fF total capacitance
• Device requires voltage driver with high output
  swing (2 3V) for a contrast ratio of about 3dB

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TX MQWM Driver Output

• Low-swing low-fanout psuedo-nmos mux used for
  speed
• Low swing amplified to provide 2.5V swing to the
  modulator
• Propagating fast pulse causes low fanout buffer
  chain
• Trade-off between number of buffers (jitter
  performance) and power consumption due to static
  power of psuedo-nmos mux
• Modulator bias voltage limited by decoupling
  transistors

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Optical to Electrical Conv.

• Photo-diodes are used for conversion
• Responsivity A/W _at_ l
• Parasitics
• Current noise (shot noise, back ground
  illumination)

Vrev
Iop
Cp
In
Electrical model
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Receivers for Optical Links

• Design goals
• High gain, low input noise current, large
  bandwidth
• Short-haul parallel links
• Dense arrays of receivers
• Low power, area
• Cheap standard process

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Front End Design

• Small R
• High noise
• Large R
• Low BW

t RCp
n2 4KT / R
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Transimpedance Amp

• Low Input impedance
• CG TIA
• Shunt-shunt feed back (R or C)
• t Rf Cp / (A-1)
• Afford larger Rf
• Higher Gain (R)
• Lower thermal noise

Rf
A
A2
Cp
Example shunt-shunt res. feedback
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TIA Design

• Challenges
• High GxBW
• Stability
• Noise/speed/gain trade off
• BW0.7 bit rate (Trade off between ISI and noise)
  
• Amp. Noise
• Voltage headroom
• Post amplifier/limiter
• Power consumption

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RF CMOS Performance Trend
RF-CMOS Performance Trends P.H. Woerlee et al.
IEEE Trans. Ele. Dev., VOL. 48, NO. 8, Aug 2001
scales
Max stable gain _at_ 2GHz
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RF Performance (Cont.)
Linearity
scales
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RF FOM Trend
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Receivers for VLSI Photonics
Vdet
V1

• Diode clamp front end
• Simple, low power, area
• Needs differential input
• Low sensitivity

V2
-Vdet
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New Receiver
Vdd
di
di0 aIop I0 di1 aIop I1
Iop
Cp
Vin
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Double Sampling, Data Resolution
Vdd
Vin(t1) gt Vin(t0) ad1 1
di
Vin(t)
1 1 0 1
t0 t1 t2
time
d0 d1 d2
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Receivers Block Diagram
1.6 Gbps, 3mW, S11mA
Vdd

f1
Sense Amp
-
Vin
C1
Photodiode
Clk_1
f2
Offset

C2
Sense Amp
-
IDC
Low-Pass Filter
Clk_2
Double-Sampler
Offset
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New Generation with Timing Recovery

• Factor of 5 DeMux at the input
• 5 equally spaced phases
• Frequency and phase adjustment by 2 different
  techniques in a dual loop PLL
• First technique PClk is shifted by half bit time
  from DClk, giving one extra sample for phase
  recovery
• New technique data samples are used for phase
  recovery

5 Gbps, 70 mW
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Optical Routing

• Packet level switching performed in the optics
• Implications
• A) Consecutive packets arrive from different
  transmitters
• B) Time between packets from the same transmitter
  to a given receiver can be extremely long (i.e.
  low transition density)

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The Problem

• Different Transmitters have different
  phase/frequency w.r.t Receiver
• CDR in the receiver must re-acquire phase lock
  for each packet
• When packets are only a few Kbits, the overhead
  can easily run over 30 for conventional CDR
• Can solve fast phase acquisition by
• Resynchronize as quickly as possible for each
  packet without prior knowledge of transmitters
• Measure frequency offset between TX and RX and
  guess what the phase will be at the next packet

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CDR for ORS

• Objective
• Calibrate and correct for phase drift due to a
  max frequency offset of 100ppm
• Reduce this offset to less than 0.1ppm
• 0.01 bit offset in 100k cycles.
• The required technology
• how to acquire/track frequency offset information
  in digital format accurately
• Digital b/c analog circuits leaks over time
• Identifying and controlling quantization error

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Semi-Digital Dual Loop DLL
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2nd Order Digital DLL
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ORS System