Differential pass transistor pulsed latch

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Differential pass transistor pulsed latch

• Moo-Young Kim, Inhwa Jung, Young-Ho Kwak,
• Chulwoo Kim
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Outline

• Abstract
• Conventional flip-flops
• Proposed flip-flop design
• Simulation conditions and test bench
• Simulation results
• Conclusion

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Abstract

• This paper describes the Differential Pass
  Transistor Pulsed Latch (DPTPL) which enhances
  D-Q delay and reduces power consumption using
  NMOS pass transistors and feedback PMOS
  transistors.
• The power consumption of the proposed pulsed
  latch is reduced significantly due to the reduced
  clock load and smaller total transistor width
  compared to conventional differential flip-flops.
• The simulations were performed in a 0.13 um CMOS
  technology at 1.2V supply voltage with 1.25GHz
  clock frequency.

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• In a recent high frequency microprocessor, the
  clocking system consumed 70 of the total chip
  power consumption.
• In the clocking system, 90 of the power is
  consumed by the flip-flops.

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Conventional flip-flops

• The Master-Slave Latch (MSL) is a good candidate
  for low power applications.
• Hybrid latch flip-flop (HLFF) and semi-dynamic
  flip-flop (SDFF) have small delay at the cost of
  power consumption.
• Sense amplifier-based flip-flops (SAFF) and
  modified sense amplifier-based flip-flops (MSAFF)
  as well as differential type flip-flops.
• The ep-SFF has the advantages of lower power
  consumption and small delay.
• The modified SDFF (MSDFF) is one of the fastest
  flip-flops.

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Schematics of (a) explicit-pulsed hybrid static
flip-flop, (b) pulsed-clock generator, and (c)
pulsed generator timing diagram
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Proposed flip-flop design
Schematics of (a) differential pass transistor
pulsed latch (DPTPL) and (b) pulsed clock
generator
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Simulation conditions and test bench

• First, all flip-flops are simulated in a 0.13 um
  CMOS technology at 100?C with 1.2V supply voltage
  and normal process corners. The operating clock
  frequency
• in this simulation is 1.25GHz.
• For fair comparison of simulation results, all of
  the flip-flops are optimized to have minimum ED
  with the same output load of 25fF.
• Secondly, for chip testing, Operating frequency
  in this simulation is 1GHz.

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Power and delay measurement test bench for
overall comparison
On-chip delay measurement block diagram
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Layout of overall block diagram for chip test
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Simulation results
Signal waveforms of DPTPL
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Delay comparison conventional versus proposed
flip-flops
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Overall power comparison
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General characteristics
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Conclusion

• DPTPL, utilizing the strong drivability of NMOS
  with positive feedback PMOS transistors, enables
  faster operation than their conventional
  counterparts.
• It also has an advantage of lower power
  consumption mainly due to simplicity and smaller
  clock load, and total gate width.
• DPTPL reduces ED by 45.5 over ep-SFF, which
  have
• the best characteristics in our simulations
  among the conventional flip-flops.