TAP Controller for Cell-Based Design

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TAP Controller for Cell-Based Design

• Myrna Bussiere, Project Leader
• Meagan Morrell

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Purpose

• To develop and implement a Test Access Port (TAP)
  Controller for use in the IEEE 1149.4 Boundary
  Scan tiny chip testing device
• To understand Boundary Scan and to implement test
  sequences when chip has been fabricated

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Topics of Discussion

• TAP Controller overview
• Initial design for digital logic
• Layout of digital logic using Design Architect in
  Mentor Graphics
• Simulation results from QuickSim in comparison to
  expected results
• Layout of transistor level in IC Station

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TAP Controller Overview

• 16-State simple finite state machine
• Three inputs
• Nine outputs

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Initial Design Process

• Assigned 4-bit binary codes to each state of the
  TAP Controller
• Produced a state table
• Karnaugh maps were then derived
• Simplified Boolean expressions were found
• Digital logic design was formed

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State Table Diagram
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Digital Logic Design
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Transistor Level of Gates
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Transistor Level of D Flip-Flop
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Simulation Results

• Clock Frequency 200ns
• Low Power Consumption
• Contains about 450 transistors
• Total chip allows for 70,000 transistors

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Simulation Results
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Layout Design Process

• Attempted to route manually to save space
• Too time consuming, and many errors occurred
• Used AutoRoute
• Optimized space
• Fast and no errors

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IC Station Layout
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Layered Layout
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Detailed Layer Level
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TAP Area Compared to Total Chip Area
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Full Projected Layout of Tiny Chip
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Summary

• The TAP Controller for cell-based design has been
  successfully designed and laid out using the
  mentor graphics program
• We have also tested it using two methods
• It has passed both tests successfully and with no
  errors

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Next Steps

• Mach TA Simulation
• Add one more ABM to full layout
• Route all sub-components together in full layout
• Submission to MOSIS for fabrication