68HC11 Assembly Language Introduction

1
68HC11 Assembly LanguageIntroduction

• Programmers model
• Addressing Modes
• Commonly used Instructions
• Examples
• Machine Code

2
Programmers Model
Condition code register
3
Memory Addressing
address
contents
Data transfer between CPU and memory involves
address bus and data bus
address bus lines
CPU
memory
data bus lines
The 68HC11 has an 8-bit data bus and can access
only one memory byte at a time
The 68HC11 has an address bus of 16 signal lines
and can address the rangefrom 000016 to FFFF16.
Memory Map
4
Prefix for number representation
Base
Prefix
_at_ nothing
binary octal decimal hexadecimal
Note Some assemblers use
5
6 Addressing Modes

• Immediate (IMM)
• Direct (DIR)
• Extended (EXT)
• Index (INDX, INDY)
• Inherent (INH)
• Relative (REL)

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Immediate Mode

• The actual operand is contained in the byte or
  bytes immediately following the instruction
  opcode
• LDAA 22
• ADDA _at_32
• LDAB 17
• LDD 1000

Refer to p. 625, 706
7
Direct mode A one-byte value is used as the
address of a memory operand (located in on-chip
SRAM) ADDA 10 SUBA 20 LDD 30 Extended
mode A two-byte value is used as the address of a
memory operand LDAA 1000 LDX 1000 ADDD
1030 Indexed mode The sum of one of the index
registers and an 8-bit value is used as the
address of a memory operand ADDA 10,X LDAA
3,Y
Little Endian Big Endian (p.17)
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Inherent mode - Operands are implied by the
instruction - No address information is
needed ABA INCB INX Relative mode - Used
in branch instructions to specify the branch
target - Specified using either a 16-bit value
or a label (preferred) ... BEQ there ADDA
10 ... there DECB
Symbolic label
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Commonly-used instructions

• The LOAD instruction places or copies a value
  from a memory location into a register (refer to
  Table 1.2)
• The ADD instruction (Table 1.3)
• The SUB instruction (Table 1.4)
• The STORE instruction

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The 68HC11 Machine Code
A 68HC11 instruction consists of 1 to 2 bytes of
opcode and 0 to 3 bytes of operand
information Examples Machine
instructions Assembly instruction (in hex
format) LDAA 29
86 1D STAA 00 97
00 ADDA 02 9B
02 STAA 01 97
01 INY 18 08
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Decoding machine language instructions Procedure

• Step 1 Compare the first one or two bytes with
  the opcode table to identify the corresponding
  assembly mnemonic and format.
• Step 2 Identify the operand bytes after the
  opcode field.
• Step 3 Write down the corresponding assembly
  instruction.
• Step 4 Repeat step 1 to 3 until the machine code
  file is exhausted.

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OPcode Sample

• machine code assembly instruction format
• 01 NOP
• 86 LDAA IMM
• 96 LDAA DIR
• C6 LDAB IMM
• D6 LDAB DIR
• CC LDD IMM
• DC LDD DIR
• 8B ADDA IMM
• 9B ADDA DIR
• CB ADDB IMM
• DB ADDB DIR
• C3 ADDD IMM
• D3 ADDD DIR
• 97 STAA DIR
• D7 STAB DIR
• DD STD DIR

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Decoding Example
96 30 8B 07 97 30 96 31
Instruction 1. Step 1. The first byte 96
corresponds to the instruction LDAA DIR. Step 2.
The second byte, 30, is the direct address. Step
3. Therefore, the first instruction is LDAA 30.
Instruction 2. Step 1. The third byte (8B)
corresponds to the instruction ADDA IMM. Step 2.
The immediate value is 07. Step 3. Therefore, the
second instruction is ADDA 07. Instruction 3.
Step 1. The fifth byte (97) corresponds to the
instruction STAA DIR. Step 2. The DIR address is
the next byte 30. Step 3. Therefore, the third
instruction is STAA 30. Instruction 4. Step 1.
The seventh byte (96) corresponds to the
instruction LDAA DIR. Step 2. The DIR value is
the next byte 31. Step 3. Therefore, the four
instruction is LDAA 31.
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The 68HC11 Instruction Execution Cycle -
Perform a sequence of read cycles to fetch
instruction opcode byte and address
information. - Optionally perform read
cycle(s) required to fetch the memory
operand. - Perform the operation specified by the
opcode. - Optionally write back the result to a
register or a memory location. - Consider the
following 3 instructions Assembly
instruction Memory location Opcode LDAA
2000 C000 B6 20 00 ADAA 3000 C003 BB 30
00 STAA 2000 C006 B7 20 00
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Executing LDAA 2000
Step 1. Place the value in PC on the address bus
with a request to read the contents of
that location. Step 2. The opcode byte B6 at
C000 is returned to the CPU and PC is
incremented by 1.
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Executing LDAA 2000
Step 3. CPU performs two read cycles to obtain
the extended address 2000 from locations C001
and C002. At the end the value of PC is
incremented to C003
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Executing LDAA 2000
Step 4. The CPU performs another read to get the
contents of the memory location at 2000, which
is 19. The value 19 will be loaded into
accumulator A.
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Homework

• Chap 1 Exercise
• 11, 13, 14, 16, 17, 19, 22, 23, 24, 25
• Due ?