Shukri Souri, Kaustav Banerjee, and Krishna Saraswat

1
Multiple Si Layer ICs Motivation, Performance
Analysis, and Design Implications

• Shukri Souri, Kaustav Banerjee, and Krishna
  Saraswat
• Stanford University
• Amit Mehrotra
• University of Illinois-Urbana Champaign

Funding Sources DARPA and MARCO IFC
2
Presentation Outline

• Why 3-D ICs?
• 3-D IC Performance Simulations
• Technologies for 3-D ICs
• Thermal Analysis
• Design Implications
• Summary

3
Why 3-D ICs?

• Increasing Chip Size and Interconnect Delay
• Limitations of Cu/Low-k
• Limitations of Repeaters
• Vehicle for Systems Integration

4
Why 3-D ICs?
Interconnect Delay is Increasing (NTRS 97)
5
Why 3-D ICs?
Will better materials like copper and low-k
dielectrics solve the interconnect problem?
6
Why 3-D ICs?
Low-k Dielectrics
Old dielectric SiO2 K 4 New dielectric Silk K
2.5
The difference is not even a factor of 2
7
Why 3-D ICs?
Limit of Low-k Dielectrics (Air K 1)
Air-Gap Interconnect Structure
8
Why 3-D ICs?
Cu Resistivity Effect of Scaling

• Effect of Cu diffusion Barrier
• Barriers have higher resistivity
• Barriers cant be scaled below a minimum
  thickness

• Effect of Electron Scattering
• Reduced mobility as dimensions decrease

• Effect of Higher Frequencies
• Carriers confined to outer skin increasing
  resistivity

Problem is worse than anticipated in the ITRS
1999 roadmap
9
Why 3-D ICs?
Can we solve the problem by using more repeaters?
10
Why 3-D ICs?
Fraction of Chip Area Used by Repeaters
Rents Exponents

• As much as 27 of the chip area at 50 nm node is
  likely to be occupied by repeaters.

11
Why 3-D ICs?
Novel Design Architectures needed to Minimize
Interconnect Delay in DSM ICs
12
3D ICs with Multiple Active Si Layers

• Advantages
• Interconnect length and therefore R, L, C can be
  minimized by stacking active Si layers
• Reduce Chip Area
• Disparate technology integration possible, e.g.,
  memory logic, optical I/O, etc.

Repeaters optical I/O devices
Gate
n/p
n/p
VILIC
M4
M3
M2
M1
Memory, Analog
Gate
T2
n/p
n/p
M2
M1
Gate
Via
T1
n/p
n/p
Logic
13
Presentation Outline

• Why 3-D ICs?
• 3-D IC Performance Simulations
• Technologies for 3-D ICs
• Thermal Analysis
• Design Implications
• Summary

14
Performance Analysis Strategy

• Estimate Chip Area
• Estimate Interconnect Delay

• Chip Area Determined from Wiring Requirement
• Used 50 nm NTRS 1997 Data

15
Wire Length Distribution For 3-D ICs

• T k Np T1 T2 - Tint
• T1 T2 k (N/2)p
• Text, i Ti - Tint/2 k 2p-1 (N/2)p

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Wire-length Distribution of 3-D IC
Microprocessor Example from NTRS 50 nm
Node Number of Gates 180 million Minimum
Feature Size 50 nm Number of wiring levels,
9 Metal Resistivity, Copper 1.673e-6
Ohm-cm Dielectric Constant, Polymer er 2.5
Single Layer
2 Layers
Replace horizontal by vertical interconnect
Vertical inter-layer connections reduce metal
wiring requirement
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Chip Area Estimation

• Placement of a wire in a tier is determined by
  some constraint, e.g., maximum allowed RC delay

• Wiring Area wire pitch x total length
• Areq plocLtot_loc psemiLtot_semi
  pglobLtot_glob

• Ltot calculated from wire-length distribution

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2 Active Layer Results

• Upper tiers pitches are reduced for constant chip
  frequency, fc
• Less wiring needed
• Almost 50 reduction in chip area

2D-1Layer 7.9 cm2
3D-2Layer 4.0 cm2
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Improved Performance with Area

• Higher fc obtained from larger wire pitch
• Results in increase in chip area
• Cannot increase fc indefinitely

20
Delay of Scaled 2D and 3D ICs

• Moving repeaters to upper active tiers reduces
  interconnect delay by 9.
• 3D (2 Si layers) shows significant delay
  reduction (64).
• Increasing the number of metal levels in 3D
  improves interconnect delay by another 35.

21
More Than 2 Active Layers

• Simulation based on data from NTRS (50 nm)
• Further improvement in delay achieved

22
Presentation Outline

• Why 3-D ICs?
• 3-D IC Performance Simulations
• Technologies for 3-D ICs
• Thermal Analysis
• Design Implications
• Summary

23
3D Technologies
Wafer Bonding
Solid Phase Crystallization of ?-Si
Epitaxial Lateral Overgrowth
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Ge Seeded Lateral Crystallization

• Concept
• Locally induce nucleation
• Grow laterally, inhibiting additional
  nucleation
• Build MOSFET in a single grain

25
Single Grain Transistors in Ge Induced
Crystallized Si
Mobility
ID-VG of 0.1 µm NMOS
SGT
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Ni Seeded Lateral Crystallization

• Initially transistor fabricated in ?-Si
• Ni seeding for simultaneous crystallization and
  dopant activation
• Low thermal budget (450C)
• Devices can be fabricated on top of a metal line

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Presentation Outline

• Why 3-D ICs?
• 3-D IC Performance Simulations
• Technologies for 3-D ICs
• Thermal Analysis
• Design Implications
• Summary

28
Thermal Issues in 3D ICs
Power Dissipation for 2D

• 1-D model used to calculate die temperature

29
3D Examples for Thermal Study

• Case A Heat dissipation is confined to one
  surface

• Case B Heat dissipation possible from 2 surfaces.

30
Die Temperature Estimation (50 nm)
Die Temperatures Estimated for Maximum Performance
Advanced heat-sinking technologies can reduce the
die temperatures for 2-D and 3-D ICs
31
Presentation Outline

• Why 3-D ICs?
• 3-D IC Performance Simulations
• Technologies for 3-D ICs
• Thermal Analysis
• Design Implications
• Summary

32
3D ICs Implications for Circuit Design

• Critical Path Layout By vertical stacking, the
  distance between logic blocks on the critical
  path can be reduced to improve circuit
  performance.
• Microprocessor Design on-chip caches on the
  second active layer will reduce distance from the
  logic and computational blocks.
• Repeaters Some chip area can be saved by
  placing repeaters ( 10,000 for high performance
  circuits) on the higher active layers.

33
3D ICs Implications for Circuit Design

• Integration of Disparate Technologies Easier
• RF and Mixed Signal ICs Substrate isolation
  between the digital and RF/analog components can
  be improved by dividing them among separate
  active layers - ideal for system on a chip
  design.
• Optical I/Os can be integrated in the top layer
• Physical Design and Synthesis
• Placement and routing algorithms, and hence
  synthesis algorithms and architectural choices,
  need to be suitably modified.

34
Summary

• Cu/low k alone will not solve DSM interconnect
  problems.
• New design architectures will be needed.
• Performance modeling of 3-D ICs shows
  significant improvement over 2-D.
• SPC of amorphous Si and Wafer Bonding are
  promising techniques to implement 3-D ICs.
• Thermal issues in 3-D ICs may require innovative
  packaging solutions.

35
Determination of Wire-length Distribution

• Conservation of I/Os
• TA TB TC TA-to-B TA-to-C TB-to-C TABC

Block A with NA gates
TA TB TA-to-B TAB TB TC TB-to-C TBC

• Values of T within a block or collection of
  blocks are calculated using Rents rule, e.g.,
• TA k (NA) P
• TABC k (NA NB NC) P
• Recursive use of Rents rule gives wire-length
  distribution for the whole chip

Block B
Block C
Rents Rule T k Np
Ref Davis Meindl, IEEE TED, March 1998