Modeling SingleEvent Effects in Strained Si Technologies

1
Modeling Single-Event Effects in Strained Si
Technologies

• Scott Thompson,
• University of Florida
• Research Advanced Devices Under Strain (RADiUS)
• Present by Yongke Sun

2
Outline

• Silicon mega trends
• Modeling Single-Event Effects in Strained Si
  Devices
• Future direction
• Summary

3
Outline

• Silicon mega trends
• Modeling Single-Event Effects in Strained Si
  Devices
• Future direction
• Summary

4
Transistor Has Come a Long Way

1947 transistorBell Labs
1958, IC,TI
35 nm
Source
Drain
Drain
Source
37nm
Channel
NiSi
Gate
1947 Transistor 100mm
United States Patent 1930-3 J.E. Lilienfeld
SiGe
1961, Planar IC
Si1-xGex
Influenza virus Source CDC
5
Conventional Scaling
Original
Scaled Device
LE scaling - drove industry 40 years - has ended
6
Density Scaling Minimal LG Scaling
Device structure roadmap clear for this decade
Planar CMOS
7
Strained Si Is The New Vector
A 90nm Logic Technology Futuring 50nm Strained
Silicon Channel Transistors IEEE International
Electron Devices Meeting (IEDM), 2002
AMAT Stress Management in Sub-90-nm
Transistors Abstract This brief focuses on the
physical characteristics of three dielectric
which can induce a significant degree of tensile
or compressive stress in the channel of a
sub-90-nm node MOS structure.
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Why Strain Impressive Performance
2004 IEDM Intel
9
Many Low Cost Methods to Induce Strain
Stress Memorization
TSMC
IBM
Stress metal in contact
IBM
Compressive Nitride
Tensile Nitride
Gate
HARP ILDO


Gate
Gate
S
D
SiGe
STI
NMOS
PMOS

AMAT
HARP STl
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Motivation Many Ways to Do Strain
Intel 2004 EDL TI 2004 VLSI AMAT 2004 IEDM IBM
2005 VLSI TSMC/Freescalse 2005 Samsung 2005 VLSI
Nitride
a-Si
a-Si
Gate
Gate
Removable film pre-anneal
Post
salicide
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Mobility vs. Stress Scalable Roadmap
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Outline

• Silicon mega trends
• Modeling Single-Event Effects in Strained Si
  Devices
• Future direction
• Summary

13
Modeling Scope

• NSF, SRC and AMD, AMAT, IBM, Intel, TSMC, TI, UMC
  funded device modeling/characterization work
• Single event transient in strained Semiconductors
• High Strained (1-2GPa) Si
• Calibrate to State-of-the-art uniaxial strained
  Si (90-32nm)
• 4 sets of industrial samples
• Model SET Future strained devices
• Strained Ge transistor, SiGe, GaAs MOSFETs
• Alternate crystal (110) wafers (IBMs HOT
  technology)

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Single Event Effect in Strained Si
E
Electron-hole pair generation energy
Eg
eV
k

• G. Bertuccio and D. Maiocchi
• JAP 92, 1248 (2002)

Dynamics in single event transients such as
carrier collection and recombination depends on
density of states, effective masses, and carrier
wave properties Band Structure.
Strained Si
Unstrained Si
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6 Band kp Valence Band Calculations
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3 Masses are Important
Out of Plane Large for quantum confinement
requirement
Channel Direction Small m for high ID
to Channel Large for high density-of-states
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6 Band K P Including Confinement
Schrodingers Equation and Poissons Equation
solved self-consistently using the
Finite-Difference Method.
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Full Transport Model Calculation of Density of
States
Si is confined in kz direction. 2-dimensional
density of state is given by
And total charge density over all possible bands
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Density of States Top Valence Band
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Wafer Bending Jig
Force
Force
Flexure based four point bending jig. NSF
funding for temperature control of 4-point
bending from 4K to 400K. Unique sample
preparation allows for stress 1GPa.
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Sample Preparation Allow 1GPa of Stress
Working on 1.5 to 2.0 GPa for later this year
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Mobility Enhancement / Long Short Devices
0.4
0.35
0.3
0.25
Dmn / mn
0.2
0.15
Long Channel
Short Channel
Lochtefeld et al. EDL 2001
0.1
Bradley et al. TED 2001
H Irei et al. IEDM 2004
C Gallon et al SSE 2004
0.05
Linear (Short Channel)
0
0
200
400
600
800
1000
1200
Stress (MPa)
Extract stress altered mobility versus stress
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110 Hot Topic To Enhance Hole Mobility
(110) Substrate
(100) Substrate
__ lt111gt
__ lt112gt
_ lt001gt
_ lt110gt
_ lt112gt
lt010gt
lt100gt
__ lt111gt
_ lt110gt
lt110gt
Notch
Notch
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Hole mobility Surface Orientation
250
Mobility / cm2/V.sec
With Gamiz surface roughness model
200
150
100
Sato, 1969
With Fischettis surface roughness model
50
0
(001) (112) (111)
(110)
Surface Orientation
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Si and Ge Band Structure
Constant energy surfaces (warping) shows strain
significantly alters carrier effective mass
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Bulk GaAs Band Structure
GaAs under (001) electric confinement
lt111gt
ml 1.9 m0
kz
kz
ky
mt 0.19 m0
kx
L6 ellipsoidal, mz 0.27 m0
G6 spherical, m 0.067 m0
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Si, Ge, III-V Including Strain Uniaxial
Strained carrier effective mass
Si lt110gt compressive
Ge lt110gt compressive
GaAs lt110gt compressive
4x lower mass for uniaxial strained Ge. 2x lower
mass for GaAs
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Si, Ge, III-V Including Strain Biaxial
Ge Tensile Biaxial
Si Tensile Biaxial
GaAs Tensile Biaxial
Masses for Biaxial strain are all 2-3X higher
than uniaxial strained (True for Si/Ge, GaAs)
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Physics of Reduced Leakage Current
vacuum
Electron Affinity
Compressive
Tensile
Drawing of the conduction and valence band shift
vs. strain. For tensile strain D2 moves to lower
energy increasing the Si electron affinity and
SiO2 barrier height.
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Slope ?IG(?)/IG(0) Contains Information About
Build in Stress
?IG(?)/IG(0)
Slope
Sample data Extract Slope as a Function of VG
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d?IG(?)/IG(0)/d? versus VG
Repopu-lation
Deviation from Best Fitting
( ?d , ?u ) 10
(1.141, 10.5) 5 (1.075, 10.0) 0
(1.018, 9.64) -5 (0.946, 9.10) -10
(0.873, 8.61)
Small slope SiO2 Barrier height
Gate Voltage / V
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Conclusions

• Strained semiconductors are mainstream
• 1GP stress in production at 65nm
• High stress on future nodes
• Strain completely changes the band structure
• Alters transport properties
• SET charge collection
• Have strain altered band structure for Si, Ge,
  GaAs etc.
• Next step is to link with FLOOPS/FLOODS