MediaNet Workshop

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Video Compression and StreamingHigh end video
encoding

• MediaNet Workshop
• 23rd November, 2005, Brussels

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Outline

• Main requirements for next generation of video
  encoders and possible architectures
• Selected architecture overview
• New multi format/ multi standard /multi
  application IC
• Main outcomes of the project

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Main requirements for next generation of video
encoders and possible architectures
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Main requirements for new CODECs

• Quickly usable in products at an attractive cost
• Sufficient performances (speed, power supply)
• Compatible with a cost-efficient product
  architecture
• Multi-standard, on-board up-gradable
• Quickly available
• Long term solution to capitalize on products
  development effort
• Software reusability in the long term

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Overview of possible architectures

• Possible architectures
• Software architectures
• Very high speed simple CPU (single ALU)
• Sophisticated CPU (Pentium, MIPS R12000A)
• Very Long Instruction Word CPU
• CPU with extended instructions
• Mixed Hardware/Software designs
• Symmetrical/Asymmetrical multiprocessor system
• Fully hardware architectures
• Dedicated task adapted hardware

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Analysis of video codecs
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Analysis of possible architectures
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Conclusion on possible architecture

• Solution 5 (Matrix of identical/specialized
  processors) with a processor core is well adapted
  to video block processing
• Mixed architecture Processor Hardware
  assistance based on matrix of identical
  processors is an optimised solution
• Independent of A/V Standards
• Reusable solution
• Suitable for several algorithms implementation
  (VLC/VLD, DCT, IDCT, Pre-processing calculation,
  motion compensation...)
• Easily up-gradable solution
• Matrix of programmable processors
• Control and assistance by a CPU Core
• Matrix of processors has poor performances for
  others tasks bit processing, high level
  application software, decision

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Selected architecture overviewVideo Processor
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Video Processor Architecture
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SIMD video co-processor

• A mesh connected SIMD array of 16 Processing
  Elements
• SIMD single instruction, multiple data
• Same instruction executed onto 16 Processing
  Elements (PE)
• PE have access to their own private memory, every
  PE can process a different set of data
• Mesh connected PE can exchange data using a X
  and a Y torus communication network

instruction
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
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SIMD video co-processor

• Video algorithm exhibit very high pixel
  parallelism
• Map very well to SIMD array pixels are
  distributed to PE and the same algorithm is
  applied to every pixels
• Mesh connected PE (XY torus) ? access to pixels
  neighbors
• For a given number of processing elements
• SIMD offers better density of processing elements
  per mm² than MIMD (multiple instance of the same
  processor)
• Instruction memory and sequencer shared among PE
• Communication between PE is simpler and more
  efficient in SIMD than in any other architecture
  (no synchronization overhead)

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New multi format / multistandard / multi
application IC architecture
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Flexible architecture requirements

• Architecture constraint
• Scalable and modular hardware (video processor)
  can be used either for encoding or decoding
  process, support different formats and standards
• Configurable blocks each processor can be
  configured by software to execute part of the
  encoding or decoding process and support
  different formats
• High efficiency parallelism of the
  encoding/decoding process on as many as possible
  blocks using as much as possible all the
  resources available
• High connectivity to memories high speed bus
  cross-bar connecting each block to external and
  internal RAMs
• Quickly available
• Reuse as much as possible existing hardware for
  encoder and decoder IC
• Develop hardware specific block only when needed
  (entropy coding, entropy decoding, Motion
  estimation, video inputs and ouptuts)

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Algorithm vs Architecture Tradeoffs
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New video encoding / decoding ICmultiformat/
multistandard/ multi application

• Operating modes
• Encode ()
• Dual decode
• Transcode ()
• Transrate
• Noise filtering
• Up down conversion
• () AVC multichip HD encoding

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High Level Architecture
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Main outcomes
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Project outcomes

• Deep analysis of requirements for new codecs in a
  changing environment, coping with
• increase of compression standards
• multiplicity of video formats
• diversity of applications
• Study of new architectures allowing
• scalability of hardware professional platforms
  to very light platforms
• margin for firmware upgrade standards and
  algorithm evolution
• Validation of such architectures
• algorithm vs architecture tradeoffs
• interoperability between Nextream coder and STM
  decoder