Processors II

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Processors II

• Lecture 21

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Conditional Branch Instructions
bltz PC ) PC 4 4imm if Rs lt 0 Opcode
1 beq PC ) PC 4 4imm if Rs Z Rt Opcode
5 bne PC ) PC 4 4imm if Rs s
Rt Opcode 4
The addition required to produce the Address of
the Next Instruction occurs inside the Next
Address Logic Circuit. The circuit is a 30-bit
adder with Cin 1. This produces the effect of
4 since the 2 LSBs are always 00. The
immediate operand is sign extended and
effectively shifted left 2-bits.
The BrType Control signal has 4 possible values.
BrType 00 will produce BrTrue 0. This
code is needed to zero the immediate operand for
all instructions that are NOT branches.
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Next Address Logic
PC31,2 1 Default option PC31,2 1
imm When instruction is branch and condition is
met PC31,28 jta When instruction is j or
jal Rs312 When the instruction is jr
SysCallAddr Start address of an operating system
routine
The IncrPC output is used by the jal instruction
to store the next address in register 31.
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The Datapath
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Building the Control Unit
The Control Unit is a combinational circuit that
has 12 inputs ( Opcode, OpcodeExt ) and 17
outputs ( Control Signals ). The Circuit is
implemented as a two-stage circuit. The First
stage is a decoder that asserts a unique signal
for each of the 22 instructions. The second stage
is a bank of OR gates that produce the 17 control
signals from the instruction signals.
The 17 control signals are RegWrite,
RegDst1,0, RegInSrc1,0 ALUSrc ALUFunc -
AddSub, LogicFn1,0, FnClass1,0 DataRead,
DataWrite PCSrc1,0, BrType1,0
For each instruction we can determine the
appropriate values for all 17 control signals.
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Control Word Table
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Determining the Instruction Rate
6.36 ns Useful.
125 Instructions Per Second.
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Multi-Cycle Operation
Instructions can be more than one cycle. In
addition, instructions can also vary in their
total cycle count.
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Resource Sharing
The main differences in the new Datapath arise
due to the fact that a single resource may now be
used more than once in different cycles.
The Instruction and Data Caches are also now
shared. Instructions are read from the Cache in
the first cycle of every instruction and placed
in a register called the Instruction Register. A
LW or SW Instruction may access the cache in any
later cycle
The addition that was performed by the Next
Address Logic is now performed by the ALU. Every
Instruction Cycle begins with The current PC
being used as an address to the Cache to Read a
word and place it in the Instruction Register.
The current PC is simultaneously passed to the
ALU (ALUSrcX 0) and a constant of 4 (ALUSrcY
00) is added to it. The new value PC4 is
stored in the PC at the same instant that the
Instruction Register is loaded. (PCSrc 11)
Holding registers must be placed at the outputs
of specific circuits to ensure that values
produced in a given clock cycle are available in
subsequent cycles.
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Overlapping Decode and Register Access
The first two cycles of every instruction will
always be Instruction Fetch and Instruction
Decode. The Control Unit cannot know the total
number of required cycles for the current
instruction until the instruction has been
fetched and decoded.
The single cycle processor performed the
Instruction Decoding in parallel with the
Register Read Access. Instructions such as Jump
do not use any values from the registers however
this is irrelevant as the JUMP instruction may
simply ignore the Register values.
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Changes in the Datapath
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Changes to the MUXs
The PC-Source Multiplexer
The Y-Source Multiplexer
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Control Signals
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The Control Word
The 20 Control Signals can be viewed as a large
20-bit number called the control word.